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? 2010 microchip technology inc. preliminary ds41418a pic16f707/pic16lf707 data sheet 40/44-pin, flash microcontrollers with nanowatt xlp and mtouch? technology
ds41418a-page 2 preliminary ? 2010 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-148-2 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2010 microchip technology inc. preliminary ds41418a-page 3 pic16f707/pic16lf707 devices included in this data sheet: high-performance risc cpu: ? only 35 single-word instructions to learn: - all single-cycle instructions except branches ? operating speed: - dc ? 20 mhz clock input - dc ? 200 ns instruction cycle ? 8k x 14 words of flash program memory ? 363 bytes of data memory (sram) ? interrupt capability ? 8-level deep hardware stack ? direct, indirect and relative addressing modes ? processor read access to program memory ? pinout compatible to other 40-pin pic16cxxx and pic16fxxx microcontrollers special microcontroller features: ? precision internal oscillator: - 16 mhz or 500 khz operation - factory calibrated to 1%, typical - software selectable 1, 2, 4 or 8 divider ? 31 khz low-power internal oscillator ? external oscillator block with: - 3 crystal/resonator modes up to 20 mhz - 3 external clock modes up to 20 mhz ? power-on reset (por) ? power-up timer (pwrt) ? oscillator start-up timer (ost) ? brown-out reset (bor): - selectable between two trip points - disabled in sleep option ? watchdog timer (wdt) ? programmable code protection ? in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? multiplexed master clear with pull-up/input pin ? industrial and extended temperature range ? high-endurance flash cell: - 1,000 write flash endurance (typical) - flash retention: >40 years - power-saving sleep mode ? operating voltage range: - 1.8v to 3.6v (pic16lf707) ? 1.8v to 5.5v (pic16f707) extreme low-power management pic16lf707 with nanowatt xlp: ? sleep mode: 20 na @ 1.8v, typical ? watchdog timer: 500 na @ 1.8v, typical ? timer1 oscillator: 600 na @ 1.8v, typical @ 32 khz mtouch? technology features: ? up to 32 channels ? two capacitive sensing modules: - acquire 2 samples simultaneously ? multiple power modes: - operation during sleep - proximity sensing with ultra low a current ? adjustable waveform min. and max. for optimal noise performance ? 1.8v to 5.5v operation (3.6v max. for pic16lf707) analog features: ? a/d converter: - 8-bit resolution and up to 14 channels - conversion available during sleep - selectable 1.024v/2.048v/4.096v voltage reference ? on-chip 3.2v regulator (pic16f707 device only) peripheral highlights: ? up to 35 i/o pins and 1 input-only pin: - high current source/sink for direct led drive - interrupt-on-pin change - individually programmable weak pull-ups ? timer0/a/b: 8-bit timer/counter with 8-bit prescaler ? enhanced timer1/3: - dedicated low-power 32 khz oscillator driver - 16-bit timer/counter with prescaler - external gate input mode with toggle and single shot modes - interrupt-on-gate completion ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? two capture, compare, pwm modules (ccp): - 16-bit capture, max. resolution 12.5 ns - 16-bit compare, max. resolution 200 ns - 10-bit pwm, max. frequency 20 khz ? addressable universal synchronous asynchronous receiver transmitter (ausart) ?pic16f707 ? pic16lf707 40/44-pin, flas h microcontrollers with nanowatt xlp and mtouch? technology
pic16f707/pic16lf707 ds41418a-page 4 preliminary ? 2010 microchip technology inc. ? synchronous serial port (ssp): - spi (master/slave) -i 2 c? (slave) with address mask ? voltage reference module: - fixed voltage reference (fvr) with 1.024v, 2.048v and 4.096v output levels - 5-bit rail-to-rail resistive dac with positive reference selection pin diagrams device program memory flash (words) sram (bytes) i/os capacitive touch channels 8-bit a/d (ch) ausart ccp timers 8/16-bit pic16f707 8192 363 36 32 14 yes 2 4/2 pic16lf707 8192 363 36 32 14 yes 2 4/2 40-pin pdip pic16f707/pic16lf707 1 2 3 4 5 6 7 8 9 10 v pp /mclr /re3 v cap (3) /ss (2) /an0/ra0 cpsa0 / an1/ra1 dacout/cpsa1/an2/ra2 cpsa2/v ref /an3/ra3 tacki/t0cki/cpsa3/ra4 v cap (3) / ss (2) /cpsa4/an4/ra5 cpsa5/an5/re0 cpsa6/an6/re1 cpsa7/an7/re2 rb6/cpsb14/icspclk rb5/an13/cpsb13/t1g/t3ck i rb4/an11/cpsb12 rb3/an9/cpsb11/ccp2 (1) rb2/an8/cpsb10 rb1/an10/cpsb9 rb0/an12/cpsb8/int v dd v ss rd2/cpsb7 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd v ss clkin/osc1/cpsb0/ra7 v cap (3) / clkout/osc2/cpsb1/ra6 t1cki/t1oso/cpsb2/rc0 ccp2 (1) /t1osi/cpsb3/rc1 tbcki/ccp1/cpsb4/rc2 scl/sck/rc3 t3g/cpsb5/rd0 cpsb6/rd1 rc5/cpsa9/sdo rc4/sdi/sda rd3/cpsa8 rd4/cpsa12 rc7/cpsa11/rx/dt rc6/cpsa10/tx/ck rd7/cpsa15 rd6/cpsa14 rd5/cpsa13 rb7/cpsb15/icspdat note 1: ccp2 pin location may be selected as rb3 or rc1. 2: ss pin location may be selected as ra5 or ra0. 3: pic16f707 only.
? 2010 microchip technology inc. preliminary ds41418a-page 5 pic16f707/pic16lf707 pin diagrams 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 cpsa2/v ref /an3/ra3 dacout/cpsa1/an2/ra2 cpsa0/an1/ra1 v cap (3) /ss (2) /an0/ra0 v pp /mclr /re3 ccp2 (1) /cpsb11/an9/rb3 icspdat/cpsb15/rb7 icspclk/cpsb14/rb6 t3cki/t1g/cpsb13/an13/rb5 cpsb12/an11/rb4 nc rc6/cpsa10/tx/ck rc5/cpsa9/sdo rc4/sdi/sda rd3/cpsa8 rd2/cpsb7 rd1/cpsb6 rd0/cpsb5/t3g rc3/sck/scl rc2/cpsb4/ccp1/tbcki rc1/cpsb3/t1osi/ccp2 (1) rc0/cpsb2/t1oso/t1cki ra6/osc2/clkout/cpsb1/v cap (3) ra7/osc1/clkin/cpsb0 v ss v ss nc v dd re2/an7/cpsa7 re1/an6/cpsa6 re0/an5/cpsa5 ra5/an4/cpsa4/ss (2) /v cap (3) ra4/cpsa3/t0cki/tacki dt/rx/cpsa11/rc7 cpsa12/rd4 cpsa13/rd5 cpsa14/rd6 cpsa15/rd7 v ss v dd v dd int/cpsb8/an12/rb0 cpsb9/an10/rb1 cpsb10/an8/rb2 44-pin qfn (8x8x0.9) pic16f707 pic16lf707 note 1: ccp2 pin location may be selected as rb3 or rc1. 2: ss pin location may be selected as ra5 or ra0. 3: pic16f707 only.
pic16f707/pic16lf707 ds41418a-page 6 preliminary ? 2010 microchip technology inc. pin diagrams 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 v ref /cpsa2/an3/ra3 dacout/cpsa1/an2/ra2 cpsa0/an1/ra1 v cap (3) /ss (2) /an0/ra0 v pp /mclr /re3 nc icspdat/cpsb15/rb7 icspclk/cpsb14/rb6 t1g/cpsb13/an13/rb5 cpsb12/an11/rb4 nc rc6/cpsa10/tx/ck rc5/cpsa9/sdo rc4/sdi/sda rd3/cpsa8 rd2/cpsb7 rd1/cpsb6 rd0cpsb5/t3g rc3//sck/scl rc2cpsb4/ccp1/tbcki rc1/cpsb3/t1osi/ccp2 (1) nc nc rc0/t1oso/t1cki/cpsb2 ra6/osc2/clkout/cpsb1/v cap (3) ra7/osc1/clkin/cpsb0 v ss v dd re2/an7/cpsa7 re1/an6/cpsa6 re0/an5/cpsa5 ra5/an4/cpsa4/ss (2) /v cap (3) ra4/cpsa3/t0cki/tacki dt/rx/cpsa11/rc7 cpsa12/rd4 cpsa13/rd5 cpsa14/rd6 v ss v dd int/cpsb8/an12/rb0 cpsb9/an10/rb1 cpsb10/an8/rb2 ccp2 (1) / cpsb11/an9/rb3 cpsa15/rd7 5 4 pic16f707 pic16lf707 44-pin tqfp note 1: ccp2 pin location may be selected as rb3 or rc1. 2: ss pin location may be selected as ra5 or ra0. 3: pic16f707 only.
? 2010 microchip technology inc. preliminary ds41418a-page 7 pic16f707/pic16lf707 table 1: 40/44-pin allo cation table for pic16f707/pic16lf707 i/o 40-pin pdip 44-pin tqfp 44-pin qfn ansel a/d dac cap sensor timers ccp ausart ssp interrupt pull-up basic ra0 2 19 19 y an0 ? ? ? ? ss (3) ? ? v cap (4) ra1 3 20 20 y an1 ? cpsa0 ? ? ? ? ? ? ? ra2 4 21 21 y an2 dacout cpsa1 ? ? ? ? ? ? ? ra3 5 22 22 y an3/ v ref v ref cpsa2 ? ? ? ? ? ? ? ra4 6 23 23 y ? ? cpsa3 t0cki/ tacki ? ? ? ? ? ? ra5 7 24 24 y an4 ? cpsa4 ? ? ? ss (3) ??v cap (4) ra6 14 31 33 y ? ? cpsb1 ? ? ? ? ? ? osc2/ clkout/ v cap (4) ra7 13 30 32 y ? ? cpsb0 ? ? ? ? ? ? osc1/ clkin rb0 33 8 9 y an12 ? cpsb8 ? ? ? ? ioc/int y ? rb1 34 9 10 y an10 ? cpsb9 ? ? ? ? ioc y ? rb2 35 10 11 y an8 ? cpsb10 ? ? ? ? ioc y ? rb3 36 11 12 y an9 ? cpsb11 ? ccp2 (2) ? ? ioc y ? rb4 37 14 14 y an11 ? cpsb12 ? ? ? ? ioc y ? rb5 38 15 15 y an13 ? cpsb13 t1g/ t3cki ? ? ? ioc y ? rb6 39 16 16 y ? ? cpsb14 ? ? ? ? ioc y icspclk/ icdclk rb7 40 17 17 y ? ? cpsb15 ? ? ? ? ioc y icspdat/ icddat rc0 15 32 34 y ? ? cpsb2 t1oso/ t1cki ? ? ? ? ? ? rc1 16 35 35 y ? ? cpsb3 t1osi ccp2 (2) ?? ??? rc2 17 36 36 y ? ? cpsb4 tbcki ccp1 ? ? ? ? ? rc3 18 37 37 ? ? ? ? ? ? ? sck/scl ? ? ? rc4 23 42 42 ? ? ? ? ? ? ? sdi/sda ? ? ? rc5 24 43 43 y ? ? cpsa9 ? ? ? sdo ? ? ? rc6 25 44 44 y ? ? cpsa10 ? ? tx/ck ? ? ? ? rc7 26 1 1 y ? ? cpsa11 ? ? rx/dt ? ? ? ? rd0 19 38 38 y ? ? cpsb5 t3g ? ? ? ? ? ? rd1 20 39 39 y ? ? cpsb6 ? ? ? ? ? ? ? rd2 21 40 40 y ? ? cpsb7 ? ? ? ? ? ? ? rd3 22 41 41 y ? ? cpsa8 ? ? ? ? ? ? ? rd4 27 2 2 y ? ? cpsa12 ? ? ? ? ? ? ? rd5 28 3 3 y ? ? cpsa13 ? ? ? ? ? ? ? rd6 29 4 4 y ? ? cpsa14 ? ? ? ? ? ? ? rd7 30 5 5 y ? ? cpsa15 ? ? ? ? ? ? ? re0 8 25 25 y an5 ? cpsa5 ? ? ? ? ? ? ? re1 9 26 26 y an6 ? cpsa6 ? ? ? ? ? ? ? re2 10 27 27 y an7 ? cpsa7 ? ? ? ? ? ? ? re3 1 18 18 ? ? ? ? ? ? ? ? ? y (1) mclr / v pp v dd 11, 32 7, 28 7,8,28 ? ? ? ? ? ? ? ? ? v dd vss 12, 31 6, 29 6, 30, 31 ? ? ? ? ? ? ? ? ? v ss note 1: pull-up activated only with external mclr configuration. 2: rc1 is the default pin location for ccp2. rb3 may be selected by changing the ccp2sel bit in the apfcon register. 3: ra5 is the default pin location for ss . ra0 may be selected by changing the sssel bit in the apfcon register. 4: pic16f707 only. v cap functionality is selectable by the vcapen bits in configuration word 2.
pic16f707/pic16lf707 ds41418a-page 8 preliminary ? 2010 microchip technology inc. table of contents 1.0 device overview ............................................................................................................ ........................................................... 11 2.0 memory organization ......................................................................................................... ....................................................... 17 3.0 resets ...................................................................................................................... ................................................................. 29 4.0 interrupts .................................................................................................................. ................................................................. 39 5.0 low dropout (ldo) voltage regulator ......................................................................................... ............................................ 49 6.0 i/o ports ................................................................................................................... ................................................................. 51 7.0 oscillator module........................................................................................................... ............................................................ 69 8.0 device configuration ........................................................................................................ ......................................................... 75 9.0 analog-to-digital converter (adc) module .................................................................................... ........................................... 79 10.0 fixed voltage reference .................................................................................................... ....................................................... 89 11.0 digital-to-analog converter (dac) module ................................................................................... ............................................ 91 12.0 timer0 module .............................................................................................................. ............................................................ 95 13.0 timer1/3 modules with gate control ......................................................................................... ................................................ 99 14.0 timera/b modules ........................................................................................................... ........................................................ 111 15.0 timer2 module .............................................................................................................. .......................................................... 115 16.0 capacitive sensing module .................................................................................................. ................................................... 117 17.0 capture/compare/pwm (ccp) module ........................................................................................... ....................................... 127 18.0 addressable universal synchronous asynchr onous receiver transmitter (ausart) ............................................... ........... 137 19.0 ssp module overview ........................................................................................................ .................................................... 157 20.0 program memory read ........................................................................................................ ................................................... 179 21.0 power-down mode (sleep) .................................................................................................... ................................................. 183 22.0 in-circuit serial programming? (icsp?) ..................................................................................... ......................................... 185 23.0 instruction set summary .................................................................................................... ..................................................... 187 24.0 development support........................................................................................................ ...................................................... 197 25.0 electrical specifications.................................................................................................. ......................................................... 201 26.0 dc and ac characteristics graphs and charts ................................................................................ ...................................... 231 27.0 packaging information...................................................................................................... ....................................................... 267 appendix a: data sheet revision history........................................................................................ ................................................. 273 appendix b: migrating from other pic? devices .................................................................................. .......................................... 273 the microchip web site ......................................................................................................... ........................................................... 281 customer change notification service ........................................................................................... .................................................. 281 customer support .............................................................................................................. ............................................................... 281 reader response ................................................................................................................ ............................................................. 282 product identification system.................................................................................................. ........................................................... 283
? 2010 microchip technology inc. preliminary ds41418a-page 9 pic16f707/pic16lf707 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic16f707/pic16lf707 ds41418a-page 10 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 11 pic16f707/pic16lf707 1.0 device overview the pic16f707/pic16lf707 devices are covered by this data sheet. they are available in 40/44-pin packages. figure 1-1 shows a block diagram of the pic16f707/pic16lf707 devices. table 1-1 shows the pinout descriptions.
pic16f707/pic16lf707 ds41418a-page 12 preliminary ? 2010 microchip technology inc. figure 1-1: pic16f707/pi c16lf707 block diagram 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 ram addr 9 addr mux indirect addr fsr reg status reg mux alu instruction decode & control timing generation osc1/clkin osc2/clkout porta portb portc portd porte ra4 ra5 rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 re0 re1 re2 8 8 timer0 ra3 ra1 ra0 8 3 ra6 ra7 rd0 rd1 rd2 rd3 rd4 rd5 rd6 rd7 rb0 rb1 rb2 rb3 rb4 rb5 rb7 an6 an0 an1 an2 an3 an4 an5 an7 synchronous sda scl ss sdo serial port sdi/ sck/ tx/ck rx/dt internal oscillator block configuration 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 ram addr addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation portb portc portd porte rc1 8 8 8 3 synchronous sda scl ss sdo serial port sdi/ sck/ internal oscillator block configuration 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) 7 addr mux fsr reg status reg mux alu instruction decode and control timing generation portb portc portd porte rc1 8 8 8 3 analog-to-digital converter rb6 synchronous sda scl ss sdo serial port sdi/ sck/ internal oscillator block configuration re3 ccp2 ccp2 ccp1 ccp1 v ref ra2 an9 an8 an10 an11 an12 an13 power-up timer oscillator start-up timer power-on reset watchdog timer mclr v dd brown-out reset v ss t0cki t1g t1cki power-up timer oscillator start-up timer power-on reset watchdog timer mclr v dd brown-out reset v ss t0cki mclr v dd v ss t0cki timer1 32 khz oscillator t1osi t1oso ldo regulator capacitive sensing module a cpsa6 cpsa0 cpsa1 cpsa2 cpsa3 cpsa4 cpsa7 cpsa8 cpsa9 cpsa10 cpsa11 cpsa12 cpsa13 cpsa14 cpsa15 cpsa5 flash program memory ram t3g t3cki timer1 timer2 timer3 timera timerb ausart tacki tbcki cpsb6 cpsb0 cpsb1 cpsb2 cpsb3 cpsb4 cpsb7 cpsb8 cpsb9 cpsb10 cpsb11 cpsb12 cpsb13 cpsb14 cpsb15 cpsb5 capacitive sensing module b digital-to-analog dacout converter
? 2010 microchip technology inc. preliminary ds41418a-page 13 pic16f707/pic16lf707 table 1-1: pic16f707/pic16l f707 pinout description name function input type output type description ra0/an0/ss /v cap ra0 ttl cmos general purpose i/o. an0 an ? a/d channel 0 input. ss st ? slave select input. v cap power power filter capacitor for voltage regulator (pic16f only). ra1/an1/cpsa0 ra1 ttl cmos general purpose i/o. an1 an ? a/d channel 1 input. cpsa0 an ? capacitive sensing a input 0. ra2/an2/cpsa1/dacout ra2 ttl cmos general purpose i/o. an2 an ? a/d channel 2 input. cpsa1 an ? capacitive sensing a input 1. dacout ? an voltage reference output. ra3/an3/v ref /cpsa2 ra3 ttl cmos general purpose i/o. an3 an ? a/d channel 3 input. v ref an ? a/d voltage reference input. cpsa2 an ? capacitive sensing a input 2. ra4/cpsa3/t0cki/tacki ra4 ttl cmos general purpose i/o. cpsa3 an ? capacitive sensing a input 3. t0cki st ? timer0 clock input. tacki st ? timera clock input. ra5/an4/cpsa4/ss/ v cap ra5 ttl cmos general purpose i/o. an4 an ? a/d channel 4 input. cpsa4 an ? capacitive sensing a input 4. ss st ? slave select input. v cap power power filter capacitor for voltage regulator (pic16f only). ra6/osc2/clkout/v cap / cpsb1 ra6 ttl cmos general purpose i/o. osc2 ? xtal crystal/resonator (lp, xt, hs modes). clkout ? cmos f osc /4 output. v cap power power filter capacitor for voltage regulator (pic16f only). cpsb1 an ? capacitive sensing b input 1. ra7/osc1/clkin/cpsb0 ra7 ttl cmos general purpose i/o. osc1 xtal ? crystal/resonator (lp, xt, hs modes). clkin cmos ? external clock input (ec mode). clkin st ? rc oscillator connection (rc mode). cpsb0 an ? capacitive sensing b input 0. rb0/an12/cpsb8/int rb0 ttl cmos general purpose i/ o. individually controlled interrupt-on-change. individually enabled pull-up. an12 an ? a/d channel 12 input. cpsb8 an ? capacitive sensing b input 8. int st ? external interrupt. rb1/an10/cpsb9 rb1 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an10 an ? a/d channel 10 input. cpsb9 an ? capacitive sensing b input 9. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels
pic16f707/pic16lf707 ds41418a-page 14 preliminary ? 2010 microchip technology inc. rb2/an8/cpsb10 rb2 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an8 an ? a/d channel 8 input. cpsb10 an ? capacitive sensing b input 10. rb3/an9/cpsb11/ccp2 rb3 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an9 an ? a/d channel 9 input. cpsb11 an ? capacitive sensing b input 11. ccp2 st cmos capture/compare/pwm2. rb4/an11/cpsb12 rb4 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an11 an ? a/d channel 11 input. cpsb12 an ? capacitive sensing b input 12. rb5/an13/cpsb13/t1g/t3cki rb5 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an13 an ? a/d channel 13 input. cpsb13 an ? capacitive sensing b input 13. t1g st ? timer1 gate input. t3cki st ? timer3 clock input. rb6/icspclk/icdclk/cpsb14 rb6 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. icspclk st ? serial programming clock. icdclk st ? in-circuit debug clock. cpsb14 an ? capacitive sensing b input 14. rb7/icspdat/icddat/cpsb15 rb7 ttl cmos general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. icspdat st cmos icsp? data i/o. icddat st ? in-circuit data i/o. cpsb15 an ? capacitive sensing b input 15. rc0/t1oso/t1cki/cpsb2 rc0 st cmos general purpose i/o. t1oso xtal xtal timer1 oscillator connection. t1cki st ? timer1 clock input. cpsb2 an ? capacitive sensing b input 2. rc1/t1osi/ccp2/cpsb3 rc1 st cmos general purpose i/o. t1osi xtal xtal timer1 oscillator connection. ccp2 st cmos capture/compare/pwm2. cpsb3 an ? capacitive sensing b input 3. rc2/ccp1/cpsb4/tbcki rc2 st cmos general purpose i/o. ccp1 st cmos capture/compare/pwm1. cpsb4 an ? capacitive sensing b input 4. tbcki st ? timerb clock input. rc3/sck/scl rc3 st cmos general purpose i/o. sck st cmos spi clock. scl i 2 c? od i 2 c? clock. table 1-1: pic16f707/pic16lf707 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels
? 2010 microchip technology inc. preliminary ds41418a-page 15 pic16f707/pic16lf707 rc4/sdi/sda rc4 st cmos general purpose i/o. sdi st ? spi data input. sda i 2 c? od i 2 c? data input/output. rc5/sdo/cpsa9 rc5 st cmos general purpose i/o. sdo ? cmos spi data output. cpsa9 an ? capacitive sensing a input 9. rc6/tx/ck/cpsa10 rc6 st cmos general purpose i/o. tx ? cmos usart asynchronous transmit. ck st cmos usart synchronous clock. cpsa10 an ? capacitive sensing a input 10. rc7/rx/dt/cpsa11 rc7 st cmos general purpose i/o. rx st ? usart asynchronous input. dt st cmos usart synchronous data. cpsa11 an ? capacitive sensing a input 11. rd0/cpsb5/t3g rd0 st cmos general purpose i/o. cpsb5 an ? capacitive sensing b input 5. t3g st ? timer3 gate input. rd1/cpsb6 rd1 st cmos general purpose i/o. cpsb6 an ? capacitive sensing b input 6. rd2/cpsb7 rd2 st cmos general purpose i/o. cpsb7 an ? capacitive sensing b input 7. rd3/cpsa8 rd3 st cmos general purpose i/o. cpsa8 an ? capacitive sensing a input 8. rd4/cpsa12 rd4 st cmos general purpose i/o. cpsa12 an ? capacitive sensing a input 12. rd5/cpsa13 rd5 st cmos general purpose i/o. cpsa13 an ? capacitive sensing a input 13. rd6/cpsa14 rd6 st cmos general purpose i/o. cpsa14 an ? capacitive sensing a input 14. rd7/cpsa15 rd7 st cmos general purpose i/o. cpsa15 an ? capacitive sensing a input 15. re0/an5/cpsa5 re0 st cmos general purpose i/o. an5 an ? a/d channel 5 input. cpsa5 an ? capacitive sensing a input 5. re1/an6/cpsa6 re1 st cmos general purpose i/o. an6 an ? a/d channel 6 input. cpsa6 an ? capacitive sensing a input 6. re2/an7/cpsa7 re2 st cmos general purpose i/o. an7 an ? a/d channel 7 input. cpsa7 an ? capacitive sensing a input 7. re3/mclr /v pp re3 ttl ? general purpose input. mclr st ? master clear with internal pull-up. v pp hv ? programming voltage. v dd v dd power ? positive supply. table 1-1: pic16f707/pic16lf707 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels
pic16f707/pic16lf707 ds41418a-page 16 preliminary ? 2010 microchip technology inc. v ss v ss power ? ground reference. note: the pic16f707 devices have an internal low dropout voltage regulator. an external capacitor must be connected to one of the available v cap pins to stabilize the regulator. for more information, see section 5.0 ?low dropout (ldo) voltage regulator? . the pic16lf707 devices do not have the voltage regulator and therefore no external capacitor is required. table 1-1: pic16f707/pic16lf707 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels
? 2010 microchip technology inc. preliminary ds41418a-page 17 pic16f707/pic16lf707 2.0 memory organization 2.1 program memory organization the pic16f707/pic16lf707 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack for the pic16f707/pic16lf707 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers (gprs) and the special function registers (sfrs). bits rp0 and rp1 are bank select bits. rp1 rp0 00 ? bank 0 is selected 01 ? bank 1 is selected 10 ? bank 2 is selected 11 ? bank 3 is selected each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function registers are the general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special function registers from one bank are mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file is organized as 363 x 8 bits. each register is accessed either directly or indirectly through the file select register (fsr), (refer to section 2.5 ?indirect addressing, indf and fsr registers? ). 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (refer to table 2-2). these registers are static ram. the special function registers can be classified into two sets: core and peripheral. the special function registers associated with the ?core? are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. pc<12:0> 13 0000h 0004h stack level 1 stack level 8 reset vector interrupt vector call, return retfie, retlw stack level 2 0005h on-chip 1fffh program memory page 0 page 1 07ffh 0800h 0fffh 1000h page 2 page 3 17ffh 1800h
pic16f707/pic16lf707 ds41418a-page 18 preliminary ? 2010 microchip technology inc. table 2-1: data memory ma p for pic16f707/pic16lf707 legend: = unimplemented data memory locations, read as ? 0 ?, * = not a physical register file address indirect addr. (*) 00h indirect addr. (*) 80h indirect addr. (*) 100h indirect addr. (*) 180h tmr0 01h option 81h tmr0 101h option 181h pcl 02h pcl 82h pcl 102h pcl 182h status 03h status 83h status 103h status 183h fsr 04h fsr 84h fsr 104h fsr 184h porta 05h trisa 85h tacon 105h ansela 185h portb 06h trisb 86h cpsbcon0 106h anselb 186h portc 07h trisc 87h cpsbcon1 107h anselc 187h portd 08h trisd 88h cpsacon0 108h anseld 188h porte 09h trise 89h cpsacon1 109h ansele 189h pclath 0ah pclath 8ah pclath 10ah pclath 18ah intcon 0bh intcon 8bh intcon 10bh intcon 18bh pir1 0ch pie1 8ch pmdatl 10ch pmcon1 18ch pir2 0dh pie2 8dh pmadrl 10dh reserved 18dh tmr1l 0eh pcon 8eh pmdath 10eh reserved 18eh tmr1h 0fh t1gcon 8fh pmadrh 10fh reserved 18fh t1con 10h osccon 90h tmra 110h general purpose register 16 bytes 190h tmr2 11h osctune 91h tbcon 111h 191h t2con 12h pr2 92h tmrb 112h 192h sspbuf 13h sspadd/sspmsk 93h daccon0 113h 193h sspcon 14h sspstat 94h daccon1 114h 194h ccpr1l 15h wpub 95h general purpose register 11 bytes 115h 195h ccpr1h 16h iocb 96h 116h 196h ccp1con 17h t3con 97h 117h 197h rcsta 18h txsta 98h 118h 198h txreg 19h spbrg 99h 119h 199h rcreg 1ah tmr3l 9ah 11ah 19ah ccpr2l 1bh tmr3h 9bh 11bh 19bh ccpr2h 1ch apfcon 9ch 11ch 19ch ccp2con 1dh fvrcon 9dh 11dh 19dh adres 1eh t3gcon 9eh 11eh 19eh adcon0 1fh adcon1 9fh 11fh 19fh general purpose register 96 bytes 20h 7fh general purpose register 80 bytes a0h efh general purpose register 80 bytes 120h 16fh general purpose register 80 bytes 1a0h 1efh accesses 70h ? 7fh f0h ffh accesses 70h ? 7fh 170h 17fh accesses 70h ? 7fh 1f0h 1ffh bank 0 bank 1 bank 2 bank 3
? 2010 microchip technology inc. preliminary ds41418a-page 19 pic16f707/pic16lf707 table 2-2: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets bank 0 00h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h tmr0 timer0 module register 0000 0000 0000 0000 02h (2) pcl program counter (pc) least significant byte 0000 0000 0000 0000 03h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h (2) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read xxxx xxxx uuuu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h porte ? ? ? ? re3 re2 re1 re0 ---- xxxx ---- uuuu 0ah (1),(2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (2) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if 0000 ---0 0000 ---0 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u 11h tmr2 timer2 module register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: accessible only when sspm<3:0> = 1001.
pic16f707/pic16lf707 ds41418a-page 20 preliminary ? 2010 microchip technology inc. bank 1 80h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 81h option_reg rbpu intedg tmr0cs tmr0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (2) pcl program counter (pc) least significant byte 0000 0000 0000 0000 83h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h (2) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register 1111 1111 1111 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ? ? ? ? ?1? trise2 trise1 trise0 ---- 1111 ---- 1111 8ah (1),(2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (2) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 8ch pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie 0000 ---0 0000 ---0 8eh pcon ? ? ? ? ? ?por bor ---- --qq ---- --uu 8fh t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss1 t1gss0 0000 0x00 uuuu uxuu 90h osccon ? ? ircf1 ircf0 icsl icss ? ? --10 00-- --10 uu-- 91h osctune ? ? tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 --00 0000 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 93h (3) sspmsk synchronous serial port (i 2 c mode) address mask register 1111 1111 1111 1111 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 95h wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 1111 1111 1111 1111 96h iocb iocb7 iocb6 iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 0000 0000 0000 0000 97h t3con tmr3cs1 tmr3cs0 t3ckps1 t3ckps0 ? t3sync ?tmr3on 0000 -0-0 uuuu -u-u 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 0000 0000 0000 0000 9ah tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu 9bh tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu 9ch apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 9dh fvrcon fvrrdy fvren ? ? cdafvr1 cdafvr0 adfvr1 adfvr0 x000 0000 x000 0000 9eh t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/ done t3gval t3gss1 t3gss0 0000 0x00 uuuu uxuu 9fh adcon1 ? adcs2 adcs1 adcs0 ? ? adref1 adref0 -000 --00 -000 --00 table 2-2: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: accessible only when sspm<3:0> = 1001.
? 2010 microchip technology inc. preliminary ds41418a-page 21 pic16f707/pic16lf707 bank 2 100h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h tmr0 timer0 module register 0000 0000 0000 0000 102h (2) pcl program counter?s (pc) least significant byte 0000 0000 0000 0000 103h (2) status irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 104h (2) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h tacon tmraon ? tacs tase tapsa taps2 taps1 taps0 0-00 0000 0-00 0000 106h cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 107h cpsbcon1 ? ? ? ? cpsbch3 cpsbch2 cpsbch1 cpsbch0 ---- 0000 ---- 0000 108h cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 0--- 0000 0--- 0000 109h cpsacon1 ? ? ? ? cpsach3 cpsach2 cpsach1 cpsach0 ---- 0000 ---- 0000 10ah (1),(2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh (2) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 10ch pmdatl program memory read data register low byte xxxx xxxx uuuu uuuu 10dh pmadrl program memory read address register low byte xxxx xxxx uuuu uuuu 10eh pmdath ? ? program memory read data register high byte --xx xxxx --uu uuuu 10fh pmadrh ? ? ? program memory read address register high byte ---x xxxx ---u uuuu 110h tmra timera module register 0000 0000 0000 0000 111h tbcon tmrbon ? tbcs tbse tbpsa tbps2 tbps1 tbps0 0-00 0000 0-00 0000 112h tmrb timerb module register 0000 0000 0000 0000 113h daccon0 dacen daclps dacoe ? dacpss1 dacpss0 ? ? 000- 00-- 000- 00-- 114h daccon1 ? ? ? dacr4 dacr3 dacr2 dacr1 dacr0 ---0 0000 ---0 0000 table 2-2: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: accessible only when sspm<3:0> = 1001.
pic16f707/pic16lf707 ds41418a-page 22 preliminary ? 2010 microchip technology inc. bank 3 180h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h option_reg rb p u intedg tmr0cs tmr0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h (2) pcl program counter (pc) least significant byte 0000 0000 0000 0000 183h (2) status irp rp1 rp0 to p d zdcc 0001 1xxx 000q quuu 184h (2) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h ansela ansa7 ansa6 ansa5 ansa4 ansa3 ansa2 ansa1 ansa0 1111 1111 1111 1111 186h anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 187h anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 188h anseld ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 1111 1111 1111 1111 189h ansele ? ? ? ? ? anse2 anse1 anse0 ---- -111 ---- -111 18ah (1),(2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh (2) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 18ch pmcon1 ? ? ? ? ? ? ?rd 1--- ---0 1--- ---0 18dh ? reserved ? ? 18eh ? reserved ? ? 18fh ? reserved ? ? table 2-2: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: accessible only when sspm<3:0> = 1001.
? 2010 microchip technology inc. preliminary ds41418a-page 23 pic16f707/pic16lf707 2.2.2.1 status register the status register, shown in register 2-1, contains: ? the arithmetic status of the alu ? the reset status ? the bank select bits for data memory (sram) the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 23.0 ?instruction set summary? ). note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 2-1: status: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h-1ffh) 0 = bank 0, 1 (00h-ffh) bit 6-5 rp<1:0>: register bank select bits (used for direct addressing) 00 = bank 0 (00h-7fh) 01 = bank 1 (80h-ffh) 10 = bank 2 (100h-17fh) 11 = bank 3 (180h-1ffh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw,sublw,subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw, sublw, subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
pic16f707/pic16lf707 ds41418a-page 24 preliminary ? 2010 microchip technology inc. 2.2.2.2 option register the option register, shown in register 2-2, is a readable and writable register, which contains various control bits to configure: ? timer0/wdt prescaler ? external rb0/int interrupt ?timer0 ? weak pull-ups on portb note: to achieve a 1:1 prescaler assignment for timer0, assign the prescaler to the wdt by setting psa bit of the option register to ? 1 ?. refer to section 13.3 ?timer1/3 prescaler? . register 2-2: option_reg: option register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r b pu intedg tmr0cs tmr0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 r bp u : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual bits in the wpub register bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
? 2010 microchip technology inc. preliminary ds41418a-page 25 pic16f707/pic16lf707 2.2.2.3 pcon register the power control (pcon) register contains flag bits (refer to table 3-4) to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) the pcon register bits are shown in register 2-3. register 2-3: pcon: power control register u-0 u-0 u-0 u-0 u-0 u-0 r/w-q r/w-q ? ? ? ? ? ?por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown q = value depends on condition bit 7-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs)
pic16f707/pic16lf707 ds41418a-page 26 preliminary ? 2010 microchip technology inc. 2.3 pcl and pclath the program counter (pc) is 13 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 2-2 shows the two situations for the loading of the pc. the upper example in figure 2-2 shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in figure 2-2 shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 2-2: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, ?implementing a table read? (ds00556). 2.3.2 stack all devices have an 8-level x 13-bit wide hardware stack (refer to figure 2-1). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging all devices are capable of addressing a continuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is poped off the stack. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). example 2-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 2-1: call of a subroutine in page 1 from page 0 pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto , call opcode<10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call , return , retlw and retfie instruc- tions or the vectoring to an interrupt address. note: the contents of the pclath register are unchanged after a return or retfie instruction is executed. the user must rewrite the contents of the pclath regis- ter for any subsequent subroutine calls or goto instructions. org 500h pagesel sub_p1 ;select page 1 ;(800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 900h ;page 1 (800h-fffh) sub1_p1 : ;called subroutine ;page 1 (800h-fffh) : return ;return to ;call subroutine ;in page 0 ;(000h-7ffh)
? 2010 microchip technology inc. preliminary ds41418a-page 27 pic16f707/pic16lf707 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit of the status register, as shown in figure 2-3. a simple program to clear ram location 020h-02fh using indirect addressing is shown in example 2-2. example 2-2: indirect addressing figure 2-3: direct/indirect addressing movlw 020h ;initialize pointer movwf fsr ;to ram bankisel 020h next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue ;yes continue note: for memory map detail, refer to table 2-2. data memory indirect addressing direct addressing bank select location select rp1 rp0 6 0 from opcode irp file select register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3
pic16f707/pic16lf707 ds41418a-page 28 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 29 pic16f707/pic16lf707 3.0 resets the pic16f707/pic16lf707 differentiates between various kinds of reset: a) power-on reset (por) b) wdt reset during normal operation c) wdt reset during sleep d) mclr reset during normal operation e) mclr reset during sleep f) brown-out reset (bor) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on: ? power-on reset (por) ?mclr reset ?mclr reset during sleep ?wdt reset ? brown-out reset (bor) most registers are not affected by a wdt wake-up since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations, as indicated in table 3-3. these bits are used in software to determine the nature of the reset. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. the mclr reset path has a noise filter to detect and ignore small pulses. see section 25.0 ?electrical specifications? for pulse width specifications. figure 3-1: simplified block di agram of on-chip reset circuit mclr /v pp v dd osc1/ wdt module por ost/pwrt wdtosc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter reset enable ost enable pwrt sleep brown-out (1) reset boren clkin note 1: refer to the configuration word register 1 (register 8-1). mclre
pic16f707/pic16lf707 ds41418a-page 30 preliminary ? 2010 microchip technology inc. table 3-1: status bits and their significance por bor to pd condition 0x11 power-on reset or ldo reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep table 3-2: reset condition for special registers (2) condition program counter status register pcon register power-on reset 0000h 0001 1xxx ---- --0x mclr reset during normal operation 0000h 000u uuuu ---- --uu mclr reset during sleep 0000h 0001 0uuu ---- --uu wdt reset 0000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 0000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1. 2: if a status bit is not implemented, that bit will be read as ? 0 ?.
? 2010 microchip technology inc. preliminary ds41418a-page 31 pic16f707/pic16lf707 3.1 mclr the pic16f707/pic16lf707 has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a reset does not drive the mclr pin low. voltages applied to the pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 3-2, is suggested. an internal mclr option is enabled by clearing the mclre bit in the configuration word register. when mclre = 0 , the reset signal to the chip is generated internally. when the mclre = 1 , the re3/mclr pin becomes an external reset input. in this mode, the re3/mclr pin has a weak pull-up to v dd . in-circuit serial programming is not affected by selecting the internal mclr option. figure 3-2: recommended mclr circuit 3.2 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. a maximum rise time for v dd is required. see section 25.0 ?electrical specifications? for details. if the bor is enabled, the maximum rise time specification does not apply. the bor circuitry will keep the device in reset until v dd reaches v bor (see section 3.5 ?brown-out reset (bor)? ). when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 3.3 power-up timer (pwrt) the power-up timer provides a fixed 64 ms (nominal) time-out on power-up only, from por or brown-out reset. the power-up timer operates from the wdt oscillator. for more information, see section 7.3 ?internal clock modes? . the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit, pwrte , can disable (if set) or enable (if cleared or pro- grammed) the power-up timer. the power-up timer should be enabled when brown-out reset is enabled, although it is not required. the power-up timer delay will vary from chip-to-chip and vary due to: ?v dd variation ? temperature variation ? process variation see dc parameters for details ( section 25.0 ?electrical specifications? ). 3.4 watchdog timer (wdt) the wdt has the following features: ? shares an 8-bit prescaler with timer0 ? time-out period is from 17 ms to 2.2 seconds, nominal ? enabled by a configuration bit wdt is cleared under certain conditions described in table 3-3. 3.4.1 wdt oscillator the wdt derives its time base from 31 khz internal oscillator. v dd pic ? mcu mclr r1 10 k ? c1 0.1 ? f note: the power-up timer is enabled by the pwrte bit in the configuration word 1. note: when the oscillator start-up timer (ost) is invoked, the wdt is held in reset, because the wdt ripple counter is used by the ost to perform the oscillator delay count. when the ost count has expired, the wdt will begin counting (if enabled).
pic16f707/pic16lf707 ds41418a-page 32 preliminary ? 2010 microchip technology inc. 3.4.2 wdt control the wdte bit is located in the configuration word register 1. when set, the wdt runs continuously. the psa and ps<2:0> bits of the option register control the wdt period. see section 12.0 ?timer0 module? for more information. figure 3-3: watchdog ti mer block diagram from tmr0 postscaler 8 ps<2:0> psa to tmr0 1 1 0 0 clock source to t x g divide by 512 wdte tmrxge txgss = 11 wdte wdt reset low-power wdt osc table 3-3: wdt status conditions wdt wdte = 0 cleared clrwdt command exit sleep + system clock = extrc, intosc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost
? 2010 microchip technology inc. preliminary ds41418a-page 33 pic16f707/pic16lf707 3.5 brown-out reset (bor) brown-out reset is enabled by programming the boren<1:0> bits in the configuration register. the brown-out trip point is selectable from two trip points via the borv bit in the configuration register. between the por and bor, complete voltage range coverage for execution protection can be imple- mented. two bits are used to enable the bor. when boren = 11 , the bor is always enabled. when boren = 10 , the bor is enabled, but disabled during sleep. when boren = 0x , the bor is disabled. if v dd falls below v bor for greater than parameter (t bor ) (see section 25.0 ?electrical specifica- tions? ), the brown-out situation will reset the device. this will occur regardless of v dd slew rate. a reset is not ensured to occur if v dd falls below v bor for more than parameter (t bor ). if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above v bor , the power-up timer will execute a 64 ms reset. figure 3-4: brown -out situations note: when erasing flash program memory, the bor is forced to enabled at the minimum bor setting to ensure that any code protection circuitry is operating properly. 64 ms (1) v bor v dd internal reset v bor v dd internal reset 64 ms (1) < 64 ms 64 ms (1) v bor v dd internal reset note 1: 64 ms delay only if pwrte bit is programmed to ? 0 ?.
pic16f707/pic16lf707 ds41418a-page 34 preliminary ? 2010 microchip technology inc. 3.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after por has expired, then ost is activated after the pwrt time-out has expired. the total time-out will vary based on oscillator configu- ration and pwrte bit status. for example, in ec mode with pwrte bit = 1 (pwrt disabled), there will be no time-out at all. figure 3-5, figure 3-6 and figure 3-7 depict time-out sequences. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then, bringing mclr high will begin execution immediately (see figure 3-6). this is useful for testing purposes or to synchronize more than one pic16f707/ pic16lf707 device operating in parallel. table 3-2 shows the reset conditions for some special registers. 3.7 power control (pcon) register the power control (pcon) register has two status bits to indicate what type of reset that last occurred. bit 0 is bor (brown-out reset). bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor = 0 , indicating that a brown-out has occurred. the bor status bit is a ?don?t care? and is not necessarily predictable if the brown-out circuit is disabled (boren<1:0> = 00 in the configuration word register). bit 1 is por (power-on reset). it is a ? 0 ? on power-on reset and unaffected otherwise. the user must write a ? 1 ? to this bit following a power-on reset. on a subsequent reset, if por is ? 0 ?, it will indicate that a power-on reset has occurred (i.e., v dd may have gone too low). for more information, see section 3.5 ?brown-out reset (bor)? . figure 3-5: time-out sequence on power-up (delayed mclr ): case 1 table 3-4: time-out in various situations oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024 ? t osc 1024 ? t osc t pwrt + 1024 ? t osc 1024 ? t osc 1024 ? t osc rc, ec, intosc t pwrt ?t pwrt ?? t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
? 2010 microchip technology inc. preliminary ds41418a-page 35 pic16f707/pic16lf707 figure 3-6: time-out sequence on power-up (delayed mclr ): case 2 figure 3-7: time-out sequ ence on power-up (mclr with v dd ): case 3 v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16f707/pic16lf707 ds41418a-page 36 preliminary ? 2010 microchip technology inc. table 3-5: initialization condition for registers register address power-on reset/ brown-out reset (1) mclr reset/ wdt reset wake-up from sleep through interrupt/time-out w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu tmr0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h/82h/ 102h/182h 0000 0000 0000 0000 pc + 1 (3) status 03h/83h/ 103h/183h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h xxxx xxxx xxxx xxxx uuuu uuuu portb 06h xxxx xxxx xxxx xxxx uuuu uuuu portc 07h xxxx xxxx xxxx xxxx uuuu uuuu portd 08h xxxx xxxx xxxx xxxx uuuu uuuu porte 09h ---- xxxx ---- xxxx ---- uuuu pclath 0ah/8ah/ 10ah/18ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh/8bh/ 10bh/18bh 0000 000x 0000 000x uuuu uuuu (2) pir1 0ch 0000 0000 0000 0000 uuuu uuuu (2) pir2 0dh 0000 ---0 0000 ---0 uuuu ---u (2) tmr1l 0eh xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 0fh xxxx xxxx uuuu uuuu uuuu uuuu t1con 10h 0000 00-0 uuuu uu-u uuuu uu-u tmr2 11h 0000 0000 0000 0000 uuuu uuuu t2con 12h -000 0000 -000 0000 -uuu uuuu sspbuf 13h xxxx xxxx xxxx xxxx uuuu uuuu sspcon 14h 0000 0000 0000 0000 uuuu uuuu ccpr1l 15h xxxx xxxx xxxx xxxx uuuu uuuu ccpr1h 16h xxxx xxxx xxxx xxxx uuuu uuuu ccp1con 17h --00 0000 --00 0000 --uu uuuu rcsta 18h 0000 000x 0000 000x uuuu uuuu txreg 19h 0000 0000 0000 0000 uuuu uuuu rcreg 1ah 0000 0000 0000 0000 uuuu uuuu ccpr2l 1bh xxxx xxxx xxxx xxxx uuuu uuuu ccpr2h 1ch xxxx xxxx xxxx xxxx uuuu uuuu ccp2con 1dh --00 0000 --00 0000 --uu uuuu adres 1eh xxxx xxxx uuuu uuuu uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 and pir2 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 3-2 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u .
? 2010 microchip technology inc. preliminary ds41418a-page 37 pic16f707/pic16lf707 adcon0 1fh --00 0000 --00 0000 --uu uuuu option_reg 81h/181h 1111 1111 1111 1111 uuuu uuuu trisa 85h 1111 1111 1111 1111 uuuu uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu trisc 87h 1111 1111 1111 1111 uuuu uuuu trisd 88h 1111 1111 1111 1111 uuuu uuuu trise 89h ---- 1111 ---- 1111 ---- uuuu pie1 8ch 0000 0000 0000 0000 uuuu uuuu pie2 8dh 0000 ---0 0000 ---0 uuuu ---u pcon 8eh ---- --qq ---- --uu (1,5) ---- --uu t1gcon 8fh 0000 0x00 uuuu uxuu uuuu uxuu osccon 90h --10 qq-- --10 qq-- --uu qq-- osctune 91h --00 0000 --uu uuuu --uu uuuu pr2 92h 1111 1111 1111 1111 uuuu uuuu sspadd 93h 0000 0000 0000 0000 uuuu uuuu sspmsk 93h 1111 1111 1111 1111 uuuu uuuu sspstat 94h 0000 0000 0000 0000 uuuu uuuu wpub 95h 1111 1111 1111 1111 uuuu uuuu iocb 96h 0000 0000 0000 0000 uuuu uuuu t3con 97h 0000 -0-0 0000 -0-0 uuuu -u-u txsta 98h 0000 -010 0000 -010 uuuu -uuu spbrg 99h 0000 0000 0000 0000 uuuu uuuu tmr3l 9ah xxxx xxxx uuuu uuuu uuuu uuuu tmr3h 9bh xxxx xxxx uuuu uuuu uuuu uuuu apfcon 9ch ---- --00 ---- --00 ---- --uu fvrcon 9dh q000 0000 q000 0000 q000 0000 adcon1 9fh -000 --00 -000 --00 -uuu --uu tacon 105h 0-00 0000 0-00 0000 u-uu uuuu cpsbcon0 106h 00-- 0000 00-- 0000 uu-- uuuu cpsbcon1 107h ---- 0000 ---- 0000 ---- uuuu cpsacon0 108h 00-- 0000 00-- 0000 uu-- uuuu cpsacon1 109h ---- 0000 ---- 0000 ---- uuuu pmdatl 10ch xxxx xxxx xxxx xxxx uuuu uuuu pmadrl 10dh xxxx xxxx xxxx xxxx uuuu uuuu pmdath 10eh --xx xxxx --xx xxxx --uu uuuu pmadrh 10fh ---x xxxx ---x xxxx ---u uuuu tmra 110h 0000 0000 0000 0000 uuuu uuuu table 3-5: initialization condition for registers (continued) register address power-on reset/ brown-out reset (1) mclr reset/ wdt reset wake-up from sleep through interrupt/time-out legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 and pir2 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 3-2 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u .
pic16f707/pic16lf707 ds41418a-page 38 preliminary ? 2010 microchip technology inc. tbcon 111h 0-00 0000 0-00 0000 u-uu uuuu tmrb 112h 0000 0000 0000 0000 uuuu uuuu daccon0 113h 000- 00-- 000- 00-- uuu- uu-- daccon1 114h ---0 0000 ---0 0000 ---u uuuu ansela 185h 1111 1111 1111 1111 uuuu uuuu anselb 186h 1111 1111 1111 1111 uuuu uuuu anselc 187h 1111 1111 1111 1111 uuuu uuuu anseld 188h 1111 1111 1111 1111 uuuu uuuu ansele 189h ---- -111 ---- -111 ---- -uuu pmcon1 18ch 1--- ---0 1--- ---0 u--- ---u table 3-5: initialization conditi on for registers (continued) register address power-on reset/ brown-out reset (1) mclr reset/ wdt reset wake-up from sleep through interrupt/time-out legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 and pir2 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 3-2 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . table 3-6: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (1) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu pcon ? ? ? ? ? ?por bor ---- --qq ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?, q = value depends on condition. shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation.
? 2010 microchip technology inc. preliminary ds41418a-page 39 pic16f707/pic16lf707 4.0 interrupts the pic16f707/pic16lf707 device family features an interruptible core, allowing certain events to preempt normal program flow. an interrupt service routine (isr) is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. the pic16f707 family has 16 interrupt sources, differentiated by corresponding interrupt enable and flag bits: ? timer0 overflow interrupt ? external edge detect on int pin interrupt ? portb change interrupt ? timer1 gate interrupt ? a/d conversion complete interrupt ? ausart receive interrupt ? ausart transmit interrupt ? ssp event interrupt ? ccp1 event interrupt ? timer2 match with pr2 interrupt ? timer1 overflow interrupt ? ccp2 event interrupt ? timera overflow interrupt ? timerb overflow interrupt ? timer3 overflow interrupt ? timer3 gate interrupt a block diagram of the interrupt logic is shown in figure 4-1. figure 4-1: interrupt logic tmr0if tmr0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) (1) interrupt to cpu tmr1gie tmr1gif adif adie ioc-rb0 iocb0 ioc-rb1 iocb1 ioc-rb2 iocb2 ioc-rb3 iocb3 ccp1if ccp1ie ioc-rb4 iocb4 ioc-rb5 iocb5 ioc-rb6 iocb6 ioc-rb7 iocb7 rcif rcie tmr2ie tmr2if sspie sspif txie txif tmr1ie tmr1if note 1: some peripherals depend upon the system clock for operation. since the system clock is suspended during sleep, these peripherals will not wake the part from sleep. see section 21.1 ?wake-up from sleep? . ccp2if ccp2ie tmraif tmraie tmr3if tmr3ie tmr3gif tmr3gie tmrbif tmrbie
pic16f707/pic16lf707 ds41418a-page 40 preliminary ? 2010 microchip technology inc. 4.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon register ? interrupt enable bit(s) for the specific interrupt event(s) ? peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the pie1 and pie2 registers) the intcon, pir1 and pir2 registers record individ- ual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? pc is loaded with the interrupt vector 0004h the isr determines the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 4.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is 3 instruction cycles. for asynchronous interrupts, the latency is 3 to 4 instruction cycles, depending on when the interrupt occurs. see figure 4-2 for timing details. figure 4-2: int pin interrupt timing note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in intosc and rc oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 25.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1)
? 2010 microchip technology inc. preliminary ds41418a-page 41 pic16f707/pic16lf707 4.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to section 21.0 ?power- down mode (sleep)? for more details. 4.4 int pin the external interrupt, int pin, causes an asynchronous, edge-triggered interrupt. the intedg bit of the option register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. this interrupt is disabled by clearing the inte bit of the intcon register. 4.5 context saving when an interrupt occurs, only the return pc value is saved to the stack. if the isr modifies or uses an instruction that modifies key registers, their values must be saved at the beginning of the isr and restored when the isr completes. this prevents instructions following the isr from using invalid data. examples of key registers include the w, status, fsr and pclath registers. the code shown in example 4-1 can be used to do the following. ? save the w register ? save the status register ? save the pclath register ? execute the isr program ? restore the pclath register ? restore the status register ? restore the w register since most instructions modify the w register, it must be saved immediately upon entering the isr. the swapf instruction is used when saving and restoring the w and status registers because it will not affect any bits in the status register. it is useful to place w_temp in shared memory because the isr cannot predict which bank will be selected when the interrupt occurs. the processor will branch to the interrupt vector by loading the pc with 0004h. the pclath register will remain unchanged. this requires the isr to ensure that the pclath register is set properly before using an instruction that causes pclath to be loaded into the pc. see section 2.3 ?pcl and pclath? for details on pc operation. example 4-1: saving w, status and pclath registers in ram note: the microcontroller does not normally require saving the pclath register. however, if computed goto ?s are used, the pclath register must be saved at the beginning of the isr and restored when the isr is complete to ensure correct program flow. movwf w_temp ;copy w to w_temp register swapf status,w ;swap status to be saved into w ;swaps are used because they do not affect the status bits banksel status_temp ;select regardless of current bank movwf status_temp ;copy status to bank zero status_temp register movf pclath,w ;copy pclath to w register movwf pclath_temp ;copy w register to pclath_temp : :(isr) ;insert user code here : banksel status_temp ;select regardless of current bank movf pclath_temp,w ; movwf pclath ;restore pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
pic16f707/pic16lf707 ds41418a-page 42 preliminary ? 2010 microchip technology inc. 4.5.1 intcon register the intcon register is a readable and writable register, which contains the various enable and flag bits for tmr0 register overflow, portb change and external rb0/int/seg0 pin interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. register 4-1: intcon: interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie tmr0ie inte rbie (1) tmr0if (2) intf rbif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie: portb change interrupt enable bit (1) 1 = enables the portb change interrupt 0 = disables the portb change interrupt bit 2 tmr0if: timer0 overflow interrupt flag bit (2) 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif: portb change interrupt flag bit 1 = when at least one of the portb general purpose i/o pins changed state (must be cleared in software) 0 = none of the portb general purpose i/o pins have changed state note 1: the appropriate bits in the iocb register must also be set. 2: tmr0if bit is set when timer0 rolls over. timer0 is unchanged on reset and should be initialized before clearing tmr0if bit.
? 2010 microchip technology inc. preliminary ds41418a-page 43 pic16f707/pic16lf707 4.5.2 pie1 register the pie1 register contains the interrupt enable bits, as shown in register 4-2. note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 4-2: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enable the timer1 gate acquisition complete interrupt 0 = disable the timer1 gate acquisition complete interrupt bit 6 adie: a/d converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie: synchronous serial port (ssp) interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt
pic16f707/pic16lf707 ds41418a-page 44 preliminary ? 2010 microchip technology inc. 4.5.3 pie2 register the pie2 register contains the interrupt enable bits, as shown in register 4-3. note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 4-3: pie2 ? peripheral interrupt enable register 2 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr3gie: timer3 gate interrupt flag bit 1 = enable the timer3 gate acquisition complete interrupt 0 = disable the timer3 gate acquisition complete interrupt bit 6 tmr3ie: timer3 overflow interrupt enable bit 1 = enables the timer3 overflow interrupt 0 = disables the timer3 overflow interrupt bit 5 tmrbie: timerb overflow interrupt enable bit 1 = enables the timerb interrupt 0 = disables the timerb interrupt bit 4 tmraie: timera overflow interrupt enable bit 1 = enables the timera interrupt 0 = disables the timera interrupt bit 3-1 unimplemented: read as ' 0 ' bit 0 ccp2ie: ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt
? 2010 microchip technology inc. preliminary ds41418a-page 45 pic16f707/pic16lf707 4.5.4 pir1 register the pir1 register contains the interrupt flag bits, as shown in register 4-4. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 4-4: pir1: peripheral interrupt request register 1 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmr1gif: timer1 gate interrupt flag bit 1 = timer1 gate is inactive 0 = timer1 gate is active bit 6 adif: a/d converter interrupt flag bit 1 = a/d conversion complete (must be cleared in software) 0 = a/d conversion has not completed or has not been started bit 5 rcif: usart receive interrupt flag bit 1 = the usart receive buffer is full (cleared by reading rcreg) 0 = the usart receive buffer is not full bit 4 txif: usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (cleared by writing to txreg) 0 = the usart transmit buffer is full bit 3 sspif: synchronous serial port (ssp) interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if: ccp1 interrupt flag bit capture mode : 1 = a timer1 register capture occurred (must be cleared in software) 0 = no timer1 register capture occurred compare mode : 1 = a timer1 register compare match occurred (must be cleared in software) 0 = no timer1 register compare match occurred pwm mode : unused in this mode bit 1 tmr2if: timer2 to pr2 interrupt flag bit 1 = a timer2 to pr2 match occurred (must be cleared in software) 0 = no timer2 to pr2 match occurred bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = the timer1 register overflowed (must be cleared in software) 0 = the timer1 register did not overflow
pic16f707/pic16lf707 ds41418a-page 46 preliminary ? 2010 microchip technology inc. 4.5.5 pir2 register the pir2 register contains the interrupt flag bits, as shown in register 4-5. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 4-5: pir2: peripheral interrupt request register 2 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmr3gif: timer3 gate interrupt flag bit 1 = timer3 gate is inactive 0 = timer3 gate is active bit 6 tmr3if: timer3 overflow interrupt flag bit 1 = timer3 register overflowed (must be cleared in software) 0 = timer3 register did not overflow bit 5 tmrbif: timerb overflow interrupt flag bit 1 = timerb register has overflowed (must be cleared in software) 0 = timerb register did not overflow bit 4 tmraif: timera overflow interrupt flag bit 1 = timera register has overflowed (must be cleared in software) 0 = timera register did not overflow bit 3-1 unimplemented: read as ? 0 ? bit 0 ccp2if: ccp2 interrupt flag bit capture mode 1 = a timer1 register capture occurred (must be cleared in software) 0 = no timer1 register capture occurred compare mode 1 = a timer1 register compare match occurred (must be cleared in software) 0 = no timer1 register compare match occurred pwm mode unused in this mode
? 2010 microchip technology inc. preliminary ds41418a-page 47 pic16f707/pic16lf707 table 4-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x option_reg rbpu intedg tmr0cs tmr0se psa ps2 ps1 ps0 1111 1111 1111 1111 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pie2 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie 0000 ---0 0000 ---0 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pir2 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if 0000 ---0 0000 ---0 legend: - = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by interrupts.
pic16f707/pic16lf707 ds41418a-page 48 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 49 pic16f707/pic16lf707 5.0 low dropout (ldo) voltage regulator the pic16f707 has an internal low dropout regulator (ldo) which provides operation above 3.6v. the ldo regulates a voltage for the internal device logic while permitting the v dd and i/o pins to operate at a higher voltage. there is no user enable/disable control available for the ldo, it is always active. the pic16lf707 operates at a maximum v dd of 3.6v and does not incorporate an ldo. a device i/o pin may be configured as the ldo voltage output, identified as the v cap pin. although not required, an external low-esr capacitor may be connected to the v cap pin for additional regulator stability. the vcapen<1:0> bits of configuration word 2 determines which pin is assigned as the v cap pin. refer to table 5-1. on power-up, the external capacitor will load the ldo voltage regulator. to prevent erroneous operation, the device is held in reset while a constant current source charges the external capacitor. after the cap is fully charged, the device is released from reset. for more information on recommended capacitor values and the constant current rate, refer to the ldo regulator characteristics table in section 25.0 ?electrical specifications? . table 5-2: summary of conf iguration word with ldo table 5-1: vcapen<1:0> select bits vcapen<1:0> pin 00 ra0 01 ra5 10 ra6 11 no v cap name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config2 13:8 ? ? ? ? ? ? ? ? 76 7:0 ? ? vcapen1 (1) vcapen0 (1) ? ? ? ? legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by ldo. note 1: pic16f707 only.
pic16f707/pic16lf707 ds41418a-page 50 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 51 pic16f707/pic16lf707 6.0 i/o ports there are thirty-five general purpose i/o pins available. depending on which peripherals are enabled, some or all of the pins may not be available as general purpose i/o. in general, when a peripheral is enabled, the associated pin may not be used as a general purpose i/o pin. each port has two registers for its operation. these registers are: ? trisx registers (data direction register) ? portx registers (port read/write register) ports with analog functions also have an anselx register which can disable the digital input and save power. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 6-1. figure 6-1: generic i/o port operation 6.1 alternate pin function the alternate pin function control (apfcon) register is used to steer specific peripheral input and output functions between different pins. the apfcon register is shown in register 6-1. for this device family, the following functions can be moved between different pins. ?ss (slave select) ? ccp2 q d ck data register i/o pin read portx write portx trisx data bus to peripherals anselx v dd v ss register 6-1: apfcon: alternate pin function co ntrol register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? sssel ccp2sel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ?. bit 1 sssel: ss input pin selection bit 0 =ss function is on ra5/an4/cps7/ss /v cap 1 =ss function is on ra0/an0/ss /v cap bit 0 ccp2sel: ccp2 input/output pin selection bit 0 = ccp2 function is on rc1/t1osi/ccp2 1 = ccp2 function is on rb3/ccp2
pic16f707/pic16lf707 ds41418a-page 52 preliminary ? 2010 microchip technology inc. 6.2 porta and trisa registers porta is a 8-bit wide, bidirectional port. the corresponding data direction register is trisa (register 6-3). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). example 6-1 shows how to initialize porta. reading the porta register (register 6-2) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. the trisa register (register 6-3) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 6-1: initializing porta note: the ansela register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. banksel porta ; clrf porta ;init porta banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw 0ch ;set ra<3:2> as inputs movwf trisa ;and set ra<7:4,1:0> ;as outputs register 6-2: porta: porta register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ra<7:0> : porta i/o pin bits 1 = port pin is > v ih 0 = port pin is < v il register 6-3: trisa: porta tri-state register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 trisa<7:0>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output
? 2010 microchip technology inc. preliminary ds41418a-page 53 pic16f707/pic16lf707 6.2.1 ansela register the ansela register (register 6-4) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansela bits has no affect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 6.2.2 pin descriptions each porta pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the a/d conver ter (adc), refer to the appropriate section in this data sheet. 6.2.2.1 ra0/an0/v cap the ra0 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? slave select input for the ssp (1) ? voltage regulator capacitor pin (pic16f707 only) 6.2.2.2 ra1/an1/cpsa0 the ra1 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? capacitive sensing input 6.2.2.3 ra2/an2/cpsa1/dacout the ra2 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? capacitive sensing input ? dac output register 6-4: ansela: porta analog select register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansa7 ansa6 ansa5 ansa4 ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit ?0? = bit is cleared -n = value at por ?1? = bit is set x = bit is unknown bit 7-0 ansa<7:0> : analog select between analog or digital function on pins ra<7:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. note 1: ss pin location may be selected as ra5 or ra0.
pic16f707/pic16lf707 ds41418a-page 54 preliminary ? 2010 microchip technology inc. 6.2.2.4 ra3/an3/v ref +/cpsa2 the ra3 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? voltage reference input for the a/d ? capacitive sensing input 6.2.2.5 ra4/cpsa3/t0cki/tacki the ra4 pin is configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input ? clock input for timer0 ? clock input for timera the timer0 clock input function works independently of any tris register setting. effectively, if trisa4 = 0 , the porta4 register bit will output to the pad and clock timer0 at the same time. 6.2.2.6 ra5/an4/cpsa4/ss /v cap the ra5 pin is configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input ? analog input for the a/d ? slave select input for the ssp (1) ? voltage regulator capacitor pin (pic16f707 only) 6.2.2.7 ra6/cpsb1/osc2/clkout/v cap the ra6 pin is configurable to function as one of the following: ? general purpose i/o ? crystal/resonator connection ? clock output ? voltage regulator capacitor pin (pic16f707 only) ? capacitive sensing input 6.2.2.8 ra7/cpsb0/osc1/clkin the ra7 pin is configurable to function as one of the following: ? general purpose i/o ? crystal/resonator connection ? clock input ? capacitive sensing input. note 1: ss pin location may be selected as ra5 or ra0. table 6-1: summary of registers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 adcon1 ? adcs2 adcs1 adcs0 ? ? adref1 adref0 -000 --00 -000 --00 ansela ansa7 ansa6 ansa5 ansa4 ansa3 ansa2 ansa1 ansa0 1111 1111 1111 1111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 00-- 0000 00-- 0000 cpsacon1 ? ? ? ? cpsach3 cpsach2 cpsach1 cpsach0 ---- 0000 ---- 0000 cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 cpsbcon1 ? ? ? ? cpsbch3 cpsbch2 cpsbch1 cpsbch0 ---- 0000 ---- 0000 config2 (1) ? ? vcapen1 vcapen0 ? ? ? ? ?? option_reg rbpu intedg tmr0cs tmr0se psa ps2 ps1 ps0 1111 1111 1111 1111 porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx xxxx xxxx xxxx sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 tacon tmraon ? tacs tase tapsa taps2 taps1 taps0 0-00 0000 0-00 0000 daccon0 dacen daclps dacoe ? dacpss1 dacpss0 ? ? 000- 00-- 000- 00-- legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note 1: pic16f707 only.
? 2010 microchip technology inc. preliminary ds41418a-page 55 pic16f707/pic16lf707 6.3 portb and trisb registers portb is an 8-bit wide, bidirectional port. the corresponding data direction register is trisb (register 6-6). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 6-2 shows how to initialize portb. reading the portb register (register 6-5) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. the trisb register (register 6-6) controls the portb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 6-2 shows how to initialize portb. example 6-2: initializing portb 6.3.1 anselb register the anselb register (register 6-9) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselb bits has no affect on digital output functions. a pin with tris clear and anselb set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 6.3.2 weak pull-ups each of the portb pins has an individually configurable internal weak pull-up. control bits wpub<7:0> enable or disable each pull-up (see register 6-7). each weak pull- up is automatically turned off when the port pin is configured as an output. all pull-ups are disabled on a power-on reset by the rbpu bit of the option register. 6.3.3 interrupt-on-change all of the portb pins are individually configurable as an interrupt-on-change pin. control bits iocb<7:0> enable or disable the interrupt function for each pin. refer to register 6-8. the interr upt-on-change feature is disabled on a power-on reset. for enabled interrupt-on-change pins, the present value is compared with the old value latched on the last read of portb to determine which bits have changed or mismatched the old value. the ?mismatch? outputs of the last read are or?d together to set the portb change interrupt flag bit (rbif) in the intcon register. this interrupt can wake the device from sleep. the user, in the interrupt service routine, clears the interrupt by: a) any read or write of portb. this will end the mismatch condition. b) clear the flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading or writing portb will end the mismatch condition and allow flag bit rbif to be cleared. the latch holding the last read value is not affected by a mclr nor brown-out reset. after these resets, the rbif flag will continue to be set if a mismatch is present. note: the anselb register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. banksel portb ; clrf portb ;init portb banksel anselb clrf anselb ;make rb<7:0> digital banksel trisb ; movlw b ? 11110000 ? ;set rb<7:4> as inputs ;and rb<3:0> as outputs movwf trisb ; note: when a pin change occurs at the same time as a read operation on portb, the rbif flag will always be set. if multiple portb pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state.
pic16f707/pic16lf707 ds41418a-page 56 preliminary ? 2010 microchip technology inc. register 6-5: port b: portb register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 rb<7:0> : portb i/o pin bit 1 = port pin is > v ih 0 = port pin is < v il register 6-6: trisb: po rtb tri-state register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 trisb<7:0>: portb tri-state control bit 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output register 6-7: wpub: weak pull-up portb register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 wpub<7:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global rbpu bit of the option register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output.
? 2010 microchip technology inc. preliminary ds41418a-page 57 pic16f707/pic16lf707 6.3.4 pin descriptions each portb pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the ssp, i 2 c or interrupts, refer to the appropriate section in this data sheet. 6.3.4.1 rb0/an12/cpsb8/int these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input ? external edge triggered interrupt 6.3.4.2 rb1/an10/cpsb9 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input 6.3.4.3 rb2/an8/cpsb10 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input register 6-8: iocb: interrup t-on-change portb register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iocb7 iocb6 iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 iocb<7:0>: interrupt-on-change portb control bits 1 = interrupt-on-change enabled 0 = interrupt-on-change disabled register 6-9: anselb: portb analog select register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ansb<7:0> : analog select between analog or digital function on pins rb<7:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
pic16f707/pic16lf707 ds41418a-page 58 preliminary ? 2010 microchip technology inc. 6.3.4.4 rb3/an9/cpsb11/ccp2 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input ? capture 2 input, compare 2 output, and pwm2 output 6.3.4.5 rb4/an11/cpsb12 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input 6.3.4.6 rb5/an13/cpsb13/t1g/t3cki these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input ? timer1 gate input ? timer3 clock input 6.3.4.7 rb6/icspclk/cpsb14 these pins are configurable to function as one of the following: ? general purpose i/o ? in-circuit serial programming clock ? capacitive sensing input 6.3.4.8 rb7/icspdat/cpsb15 these pins are configurable to function as one of the following: ? general purpose i/o ? in-circuit serial programming data ? capacitive sensing input note: ccp2 pin location may be selected as rb3 or rc1. table 6-2: summary of registers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 cpsbcon1 ? ? ? ? cpsbch3 cpsbch2 cpsbch1 cpsbch0 ---- 0000 ---- 0000 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x iocb iocb7 iocb6 iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 0000 0000 0000 0000 option_reg rbpu intedg tmr0cs tmr0se psa ps2 ps1 ps0 1111 1111 1111 1111 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx xxxx xxxx t3con tmr3cs1 tmr3cs0 t3ckps1 t3ckps0 ? t3sync ?tmr3on 0000 -0-0 0000 -0-0 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss1 t1gss0 0000 0x00 uuuu uxuu trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portb.
? 2010 microchip technology inc. preliminary ds41418a-page 59 pic16f707/pic16lf707 6.4 portc and trisc registers portc is a 8-bit wide, bidirectional port. the corresponding data direction register is trisc (register 6-11). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 6-3 shows how to initialize portc. reading the portc register (register 6-10) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. the trisc register (register 6-11) controls the portc pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 6-3: initializing portc the location of the ccp2 function is controlled by the ccp2sel bit in the apfcon register (see register 6-1). banksel portc ; clrf portc ;init portc banksel trisc ; movlw b?00001100? ;set rc<3:2> as inputs movwf trisc ;and set rc<7:4,1:0> ;as outputs register 6-10: port c: portc register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 rc<7:0> : portc general purpose i/o pin bits 1 = port pin is > v ih 0 = port pin is < v il register 6-11: trisc: po rtc tri-state register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output
pic16f707/pic16lf707 ds41418a-page 60 preliminary ? 2010 microchip technology inc. 6.4.1 anselc register the anselc register (register 6-12) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselc bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselc bits has no affect on digital output functions. a pin with tris clear and anselc set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instruc- tions on the affected port. 6.4.2 pin descriptions each portc pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the ssp, i 2 c or interrupts, refer to the appropriate section in this data sheet. 6.4.2.1 rc0/t1oso/t1cki/cpsb2 these pins are configurable to function as one of the following: ? general purpose i/o ? timer1 oscillator output ? timer1 clock input ? capacitive sensing input 6.4.2.2 rc1/t1osi/ccp2/cpsb3 these pins are configurable to function as one of the following: ? general purpose i/o ? timer1 oscillator input ? capture 2 input, compare 2 output, and pwm2 output ? capacitive sensing input note: the anselc register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. register 6-12: anselc: portc analog select register r/w-1 r/w-1 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 ansc<7:5> : analog select between analog or digital function on pins rc<7:5>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. bit 4-3 unimplemented: read as ? 0 ? bit 2-0 ansc<2:0> : analog select between analog or digital function on pins rc<2:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. note: ccp2 pin location may be selected as rb3 or rc1.
? 2010 microchip technology inc. preliminary ds41418a-page 61 pic16f707/pic16lf707 6.4.2.3 rc2/ccp1/cpsb4/tbcki these pins are configurable to function as one of the following: ? general purpose i/o ? capture 1 input, compare 1 output, and pwm1 output ? capacitive sensing input ? timerb clock input 6.4.2.4 rc3/sck/scl these pins are configurable to function as one of the following: ? general purpose i/o ? spi clock ?i 2 c? clock 6.4.2.5 rc4/sdi/sda these pins are configurable to function as one of the following: ? general purpose i/o ? spi data input ?i 2 c data i/o 6.4.2.6 rc5/sdo/cpsa9 these pins are configurable to function as one of the following: ? general purpose i/o ? spi data output ? capacitive sensing input 6.4.2.7 rc6/tx/ck/cpsa10 these pins are configurable to function as one of the following: ? general purpose i/o ? asynchronous serial output ? synchronous clock i/o ? capacitive sensing input 6.4.2.8 rc7/rx/dt/cpsa11 these pins are configurable to function as one of the following: ? general purpose i/o ? asynchronous serial input ? synchronous serial data i/o ? capacitive sensing input table 6-3: summary of regist ers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 00-- 0000 00-- 0000 cpsacon1 ? ? ? ? cpsach3 cpsach2 cpsach1 cpsach0 ---- 0000 ---- 0000 cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 cpsbcon1 ? ? ? ? cpsbch3 cpsbch2 cpsbch1 cpsbch0 ---- 0000 ---- 0000 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx xxxx xxxx rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ? tmr1on 0000 00-0 uuuu uu-u tbcon tmrbon ? tbcs tbse tbpsa tbps2 tbps1 tbps0 0-00 0000 0-00 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 trisc trisc7 trisc6 trisc5 trisc 4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
pic16f707/pic16lf707 ds41418a-page 62 preliminary ? 2010 microchip technology inc. 6.5 portd and trisd registers portd is a 8-bit wide, bidirectional port. the corresponding data direction register is trisd (register 6-14). setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 6-4 shows how to initialize portd. reading the portd register (register 6-13) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. the trisd register (register 6-14) controls the portd pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisd register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 6-4: initializing portd 6.5.1 anseld register the anseld register (register 6-15) is used to configure the input mode of an i/o pin to analog. setting the appropriate anseld bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anseld bits has no affect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. note: the anseld register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. banksel portd ; clrf portd ;init portd banksel anseld clrf anseld ;make portd digital banksel trisd ; movlw b?00001100? ;set rd<3:2> as inputs movwf trisd ;and set rd<7:4,1:0> ;as outputs register 6-13: port d: portd register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 rd<7:0> : portd general purpose i/o pin bits 1 = port pin is > v ih 0 = port pin is < v il
? 2010 microchip technology inc. preliminary ds41418a-page 63 pic16f707/pic16lf707 6.5.2 pin descriptions each portd pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the ssp, i 2 c or interrupts, refer to the appropriate section in this data sheet. 6.5.2.1 rd0/cpsb5/t3g these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input ? timer3 gate input 6.5.2.2 rd1/cpsb6 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input 6.5.2.3 rd2/cpsb7 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input 6.5.2.4 rd3/cpsa8 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input 6.5.2.5 rd4/cpsa12 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input register 6-14: trisd: po rtd tri-state register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 trisd<7:0>: portd tri-state control bits 1 = portd pin configured as an input (tri-stated) 0 = portd pin configured as an output register 6-15: anseld: portd analog select register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ansd<7:0> : analog select between analog or digital function on pins rd<7:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
pic16f707/pic16lf707 ds41418a-page 64 preliminary ? 2010 microchip technology inc. 6.5.2.6 rd5/cpsa13 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input 6.5.2.7 rd6/cpsa14 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input 6.5.2.8 rd7/cpsa15 these pins are configurable to function as one of the following: ? general purpose i/o ? capacitive sensing input table 6-4: summary of registers associated with portd name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets anseld ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 1111 1111 1111 1111 cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 00-- 0000 00-- 0000 cpsacon1 ? ? ? ? cpsach3 cpsach2 cpsach1 cpsach0 ---- 0000 ---- 0000 cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 cpsbcon1 ? ? ? ? cpsbch3 cpsbch2 cpsbch1 cpsbch0 ---- 0000 ---- 0000 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/ done t3gval t3gss1 t3gss0 0000 0x00 uuuu uxuu portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx xxxx xxxx trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portd.
? 2010 microchip technology inc. preliminary ds41418a-page 65 pic16f707/pic16lf707 6.6 porte and trise registers porte is a 4-bit wide, bidirectional port. the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). the exception is re3, which is input only and its tris bit will always read as ? 1 ?. example 6-5 shows how to initialize porte. reading the porte register (register 6-16) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. re3 reads ? 0 ? when mclre = 1. the trise register (register 6-17) controls the porte pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trise register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 6-5: initializing porte 6.6.1 ansele register the ansele register (register 6-18) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansele bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansele bits has no affect on digital output functions. a pin with tris clear and ansele set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. note: the ansele register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. banksel porte ; clrf porte ;init porte banksel ansele ; clrf ansele ;digital i/o banksel trise ; movlw b?00001100? ;set re<2> as an input movwf trise ;and set re<1:0> ;as outputs register 6-16: port e: porte register u-0 u-0 u-0 u-0 r-x r/w-x r/w-x r/w-x ? ? ? ? re3 re2 re1 re0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented : read as ? 0 ? bit 3-0 re<3:0> : porte i/o pin bits 1 = port pin is > v ih 0 = port pin is < v il
pic16f707/pic16lf707 ds41418a-page 66 preliminary ? 2010 microchip technology inc. 6.6.2 pin descriptions each porte pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the ssp, i 2 c or interrupts, refer to the appropriate section in this data sheet. 6.6.2.1 re0/an5/cpsa5 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input 6.6.2.2 re1/an6/cpsa6 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input 6.6.2.3 re2/an7/cpsa7 these pins are configurable to function as one of the following: ? general purpose i/o ? analog input for the adc ? capacitive sensing input register 6-17: trise: porte tri-state register u-0 u-0 u-0 u-0 r-1 r/w-1 r/w-1 r/w-1 ? ? ? ? trise3 trise2 trise1 trise0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented : read as ? 0 ? bit 3 trise3: re3 port tri-state control bit this bit is always ? 1 ? as re3 is an input only bit 2-0 trise<2:0>: re<2:0> tri-state control bits (1) 1 = porte pin configured as an input (tri-stated) 0 = porte pin configured as an output register 6-18: ansele: po rte analog select register u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 ? ? ? ? ? anse2 anse1 anse0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as ? 0 ? bit 2-0 anse<2:0> : analog select between analog or digital function on pins re<2:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
? 2010 microchip technology inc. preliminary ds41418a-page 67 pic16f707/pic16lf707 6.6.2.4 re3/mclr /v pp these pins are configurable to function as one of the following: ? general purpose input ? master clear reset with weak pull-up ? programming voltage reference input table 6-5: summary of regist ers associated with porte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 ansele ? ? ? ? ? anse2 anse1 anse0 ---- -111 ---- -111 cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 00-- 0000 00-- 0000 cpsacon1 ? ? ? ? cpsach3 cpsach2 cpsach1 cpsach0 ---- 0000 ---- 0000 porte ? ? ? ? re3 re2 re1 re0 ---- xxxx ---- xxxx trise ? ? ? ?trise3 (1) trise2 trise1 trise0 ---- 1111 ---- 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porte. note 1: this bit is always ? 1 ? as re3 is input only.
pic16f707/pic16lf707 ds41418a-page 68 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 69 pic16f707/pic16lf707 7.0 oscillator module 7.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. figure 7-1 illustrates a block diagram of the oscillator module. clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system can be configured to use an internal calibrated high-frequency oscillator as clock source, with a choice of selectable speeds via software. clock source modes are configured by the fosc bits in configuration word 1 (config1). the oscillator module can be configured for one of eight modes of operation. 1. rc ? external resistor-capacitor (rc) with f osc /4 output on osc2/clkout. 2. rcio ? external resistor-capacitor (rc) with i/o on osc2/clkout. 3. intosc ? internal oscillator with f osc /4 output on osc2 and i/o on osc1/clkin. 4. intoscio ? internal oscillator with i/o on osc1/clkin and osc2/clkout. 5. ec ? external clock with i/o on osc2/clkout. 6. hs ? high gain crystal or ceramic resonator mode. 7. xt ? medium gain crystal or ceramic resonator oscillator mode. 8. lp ? low-power crystal mode. figure 7-1: simplified pic ? mcu clock source block diagram (cpu and peripherals) osc1 osc2 sleep external oscillator lp, xt, hs, rc, ec system clock postscaler mux mux 16 mhz/500 khz 8 mhz/250 khz 4 mhz/125 khz 2 mhz/62.5 khz ircf<1:0> 11 10 01 00 fosc<2:0> (configuration word 1) internal oscillator (osccon register) 500 khz intosc 32x mux 0 1 pll pllen (configuration word 1)
pic16f707/pic16lf707 ds41418a-page 70 preliminary ? 2010 microchip technology inc. 7.2 clock source modes clock source modes can be classified as external or internal. ? internal clock source (intosc) is contained within the oscillator module and derived from a 500 khz high precision oscillator. the oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 mhz. ? external clock modes rely on external circuitry for the clock source. examples are: oscillator mod- ules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes) and resistor-capacitor (rc) mode circuits. the system clock can be selected between external or internal clock sources via the fosc bits of the configuration word 1. 7.3 internal clock modes the oscillator module has eight output frequencies derived from a 500 khz high precision oscillator. the ircf bits of the osccon register select the postscaler applied to the clock source dividing the frequency by 1, 2, 4 or 8. setting the pllen bit of the configuration word 1 locks the internal clock source to 16 mhz before the postscaler is selected by the ircf bits. the pllen bit must be set or cleared at the time of programming; therefore, only the upper or low four clock source frequencies are selectable in software. 7.3.1 intosc and intoscio modes the intosc and intoscio modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the fosc<2:0> bits in the config1 register. see section 8.0 ?device configuration? for more information. in intosc mode, osc1/clkin is available for general purpose i/o. osc2/clkout outputs the selected internal oscillator frequency divided by 4. the clkout signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. in intoscio mode, osc1/clkin and osc2/ clkout are available for general purpose i/o. 7.3.2 frequency select bits (ircf) the output of the 500 khz intosc and 16 mhz intosc, with phase locked loop enabled, connect to a postscaler and multiplexer (see figure 7-1). the internal oscillator frequency select bits (ircf) of the osccon register select the frequency output of the internal oscillator. depending upon the pllen bit, one of four frequencies of two frequency sets can be selected via software: if pllen = 1 , frequency selection is as follows: ?16 mhz ? 8 mhz (default after reset) ?4 mhz ?2 mhz if pllen = 0 , frequency selection is as follows: ?500 khz ? 250 khz (default after reset) ?125 khz ?62.5 khz there is no start-up delay before a new frequency selected in the ircf bits takes effect. this is because the old and new frequencies are derived from intosc via the postscaler and multiplexer. start-up delay specifications are located in the table 25-4 in section 25.0 ?electrical specifications? . note: following any reset, the ircf<1:0> bits of the osccon register are set to ? 10 ? and the frequency selection is set to 8 mhz or 250 khz. the user can modify the ircf bits to select a different frequency.
? 2010 microchip technology inc. preliminary ds41418a-page 71 pic16f707/pic16lf707 7.4 oscillator control the oscillator control (osccon) register (figure 7-1) displays the status and allows frequency selection of the internal oscillator (intosc) system clock. the osccon register contains the following bits: ? frequency selection bits (ircf) ? status locked bits (icsl) ? status stable bits (icss) register 7-1: osccon: os cillator control register u-0 u-0 r/w-1 r/w-0 r-q r-q u-0 u-0 ? ? ircf1 ircf0 icsl icss ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown q = value depends on condition bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ircf<1:0>: internal oscillator frequency select bits when pllen = 1 (16 mhz intosc) 11 =16mhz 10 = 8 mhz (por value) 01 =4mhz 00 =2mhz when pllen = 0 (500 khz intosc) 11 = 500 khz 10 = 250 khz (por value) 01 = 125 khz 00 = 62.5 khz bit 3 icsl: internal clock oscillator status locked bit (2% stable) 1 = 16 mhz/500 khz internal oscillator (hfiosc) is in lock. 0 = 16 mhz/500 khz internal oscillator (hfiosc) has not yet locked. bit 2 icss: internal clock oscillator status stable bit (0.5% stable) 1 = 16 mhz/500 khz internal oscillator (hfiosc) has stabilized to its maximum accuracy 0 = 16 mhz/500 khz internal oscillator (hfiosc) has not yet reached its maximum accuracy bit 1-0 unimplemented: read as ? 0 ?
pic16f707/pic16lf707 ds41418a-page 72 preliminary ? 2010 microchip technology inc. 7.5 oscillator tuning the intosc is factory calibrated but can be adjusted in software by writing to the osctune register (register 7-2). the default value of the osctune register is ? 0 ?. the value is a 6-bit two?s complement number. when the osctune register is modified, the intosc frequency will begin shifting to the new frequency. code execution continues during this shift. there is no indication that the shift has occurred. register 7-2: osctune: osci llator tuning register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frequency tuning bits 01 1111 = maximum frequency 01 1110 = ? ? ? 00 0001 = 00 0000 = oscillator module is running at the factory-calibrated frequency. 11 1111 = ? ? ? 10 0000 = minimum frequency
? 2010 microchip technology inc. preliminary ds41418a-page 73 pic16f707/pic16lf707 7.6 external clock modes 7.6.1 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations on the osc1 pin before the device is released from reset. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. 7.6.2 ec mode the external clock (ec) mode allows an externally generated logic level as the system clock source. when operating in this mode, an external clock source is connected to the osc1 input and the osc2 is available for general purpose i/o. figure 7-2 shows the pin connections for ec mode. the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 7-2: exter nal clock (ec) mode operation 7.6.3 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 (figure 7-3). the mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting. figure 7-3 and figure 7-4 show typical circuits for quartz crystal and ceramic resonators, respectively. figure 7-3: quartz crystal operation (lp, xt or hs mode) osc1/clkin osc2/clkout (1) i/o clock from ext. system pic ? mcu note 1: alternate pin functions are described in section 6.1 ?alternate pin function? . note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected. c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout
pic16f707/pic16lf707 ds41418a-page 74 preliminary ? 2010 microchip technology inc. figure 7-4: ceramic resonator operation (xt or hs mode) 7.6.4 external rc modes the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. there are two modes: rc and rcio. in rc mode, the rc circuit connects to osc1. osc2/ clkout outputs the rc oscillator frequency divided by 4. this signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. figure 7-5 shows the external rc mode connections. figure 7-5: external rc modes in rcio mode, the rc circuit is connected to osc1. osc2 becomes an additional general purpose i/o pin. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: ? threshold voltage variation ? component tolerances ? packaging variations in capacitance the user also needs to take into account variation due to tolerance of external rc components used. note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected. 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout osc2/clkout (1) c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k ? ? r ext ? 100 k ? , <3v 3 k ? ? r ext ? 100 k ? , 3-5v c ext > 20 pf, 2-5v note 1: alternate pin functions are described in section 6.1 ?alternate pin function? . 2: output depends upon rc or rcio clock mode. i/o (2) table 7-1: summary of registers associated with clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (1) config1 (1) ? cp mclre pwrte wdte fosc2 fosc1 fosc0 ? ? osccon ? ? ircf1 ircf0 icsl icss ? ? --10 qq-- --10 qq-- osctune ? ? tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 --uu uuuu legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by oscillators. note 1: see configuration word 1 (register 8-1) for operation of all bits.
? 2010 microchip technology inc. preliminary ds41418a-page 75 pic16f707/pic16lf707 8.0 device configuration device configuration consists of configuration word 1 and configuration word 2 registers, code protection and device id. 8.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 register at 2007h and configuration word 2 register at 2008h. these registers are only accessible during programming. register 8-1: conf ig1: config uration word register 1 r/p-1 r/p-1 u-1 (4) r/p-1 r/p-1 r/p-1 ? ?debug pllen ? borv boren1 boren0 bit 15 bit 8 u-1 (4) r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ?cp mclre pwrte wdte fosc2 fosc1 fosc0 bit 7 bit 0 legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13 debug : in-circuit debugger mode bit 1 = in-circuit debugger disabled, rb6/icspclk and rb7/icspdat are general purpose i/o pins 0 = in-circuit debugger enabled, rb6/icspclk and rb7/icspdat are dedicated to the debugger bit 12 pllen: intosc pll enable bit 0 = intosc frequency is 500 khz 1 = intosc frequency is 16 mhz (32x) bit 11 unimplemented: read as ? 1 ? bit 10 borv: brown-out reset voltage selection bit 0 = brown-out reset voltage (v bor ) set to 2.5 v nominal 1 = brown-out reset voltage (v bor ) set to 1.9 v nominal bit 9-8 boren<1:0>: brown-out reset selection bits (1) 0x = bor disabled (preconditioned state) 10 = bor enabled during operation and disabled in sleep 11 = bor enabled bit 7 unimplemented: read as ? 1 ? bit 6 cp : code protection bit (2) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 5 mclre: re3/mclr pin function select bit (3) 1 = re3/mclr pin function is mclr 0 = re3/mclr pin function is digital input, mclr internally tied to v dd bit 4 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire program memory will be erased when the code protection is turned off. 3: when mclr is asserted in intosc or rc mode, the internal clock oscillator is disabled. 4: mplab ? ide masks unimplemented configuration bits to ? 0 ?.
pic16f707/pic16lf707 ds41418a-page 76 preliminary ? 2010 microchip technology inc. bit 2-0 fosc<2:0>: oscillator selection bits 111 = rc oscillator: clkout function on ra6/osc2/clkout pin, rc on ra7/osc1/clkin 110 = rcio oscillator: i/o function on ra6/osc2/clkout pin, rc on ra7/osc1/clkin 101 = intosc oscillator: clkout function on ra6/osc2/clkout pin, i/o function on ra7/osc1/clkin 100 = intoscio oscillator: i/o function on ra6/osc2/clkout pin, i/o function on ra7/osc1/clkin 011 = ec: i/o function on ra6/osc2/clkout pin, clkin on ra7/osc1/clkin 010 = hs oscillator: high-speed crystal/resonator on ra6/osc2/clkout and ra7/osc1/clkin 001 = xt oscillator: crystal/resonator on ra6/osc2/clkout and ra7/osc1/clkin 000 = lp oscillator: low-power crystal on ra6/osc2/clkout and ra7/osc1/clkin register 8-1: config1: configuration word re gister 1 (continued) note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire program memory will be erased when the code protection is turned off. 3: when mclr is asserted in intosc or rc mode, the internal clock oscillator is disabled. 4: mplab ? ide masks unimplemented configuration bits to ? 0 ?. register 8-2: conf ig2: config uration word register 2 u-1 (1) u-1 (1) u-1 (1) u-1 (1) u-1 (1) u-1 (1) u-1 (1) u-1 (1) ? ? ? ? ? ? ? ? bit 15 bit 8 u-1 (1) u-1 (1) r/p-1 r/p-1 u-1 (1) u-1 (1) u-1 (1) u-1 (1) ? ? vcapen1 vcapen0 ? ? ? ? bit 7 bit 0 legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented : read as ? 1 ? bit 5-4 vcapen<1:0>: voltage regulator capacitor enable bits for the pic16lf707 : these bits are ignored. all v cap pin functions are disabled. for the pic16f707 : 00 =v cap functionality is enabled on ra0 01 =v cap functionality is enabled on ra5 10 =v cap functionality is enabled on ra6 11 = all v cap functions are disabled (not recommended) bit 3-0 unimplemented : read as ? 1 ? note 1: mplab ? ide masks unimplemented configuration bits to ? 0 ?.
? 2010 microchip technology inc. preliminary ds41418a-page 77 pic16f707/pic16lf707 8.2 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out using icsp? for verification purposes. 8.3 user id four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify mode. only the least significant 7 bits of the id locations are reported when using mplab ide. see the ? pic16f707/pic16lf707 memory programming specification? (ds41332) for more information. note: the entire flash program memory will be erased when the code protection is turned off. see the ? pic16f707/pic16lf707 memory programming specification? (ds41332) for more information.
pic16f707/pic16lf707 ds41418a-page 78 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 79 pic16f707/pic16lf707 9.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 8-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 8-bit binary result via successive approximation and stores the conversion result into the adc result register (adres). figure 9-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 9-1: adc block diagram an0 an1 an2 an4 av dd v ref + adon go/done adref = 10 adref = 0x chs<3:0> v ss an5 an6 an7 an3 an8 an9 an10 an11 an12 an13 reserved fv ref 0000 0001 0010 0011 0100 0101 0111 0110 1000 1001 1010 1011 1100 1101 1110 1111 8 adc adres adref = 11
pic16f707/pic16lf707 ds41418a-page 80 preliminary ? 2010 microchip technology inc. 9.1 adc configuration when configuring and using the adc the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? results formatting 9.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 6.0 ?i/o ports? for more information. 9.1.2 channel selection the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 9.2 ?adc operation? for more information. 9.1.3 adc voltage reference the adref bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be either v dd , an external voltage source or the internal fixed voltage reference. the negative voltage reference is always connected to the ground reference. see section 10.0 ?fixed voltage reference? for more details on the fixed voltage reference. 9.1.4 conversion clock the source of the conversion clock is software select- able via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 8-bit conversion requires 10 t ad periods as shown in figure 9-2. for correct conversion, the appropriate t ad specification must be met. refer to the a/d conversion requirements in section 25.0 ?electrical specifications? for more information. table 9-1 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result. table 9-1: adc clock period (t ad ) v s . device operating frequencies adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz fosc/2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s fosc/4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4.0 ? s fosc/8 001 400 ns (2) 0.5 ? s (2) 1.0 ? s2.0 ? s 8.0 ? s (3) fosc/16 101 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s (3) fosc/32 010 1.6 ? s2.0 ? s4.0 ? s 8.0 ? s (3) 32.0 ? s (3) fosc/64 110 3.2 ? s4.0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the f rc clock source is only recommended if the conversion will be performed during sleep.
? 2010 microchip technology inc. preliminary ds41418a-page 81 pic16f707/pic16lf707 figure 9-2: analog-to-dig ital conversion t ad cycles 9.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruc- tion is always executed. if the user is attempting to wake-up from sleep and resume in-line code execu- tion, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. please refer to section 9.1.5 ?interrupts? for more information. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) b7 b6 b5 b4 b3 b2 b1 b0 tcy to t ad conversion starts adres register is loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input t ad 0 note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the f rc oscillator is selected.
pic16f707/pic16lf707 ds41418a-page 82 preliminary ? 2010 microchip technology inc. 9.2 adc operation 9.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 9.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adres register with new conversion result 9.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adres register will be updated with the partially com- plete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 9.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. 9.2.5 special event trigger the special event trigger of the ccp module allows periodic adc measurements without software inter- vention. when this trigger occurs, the go/done bit is set by hardware and the timer1 counter resets to zero. using the special event trigger does not assure proper adc timing. it is the user?s responsibility to ensure that the adc timing requirements are met. refer to section 17.0 ?capture/compare/pwm (ccp) module? for more information. 9.2.6 a/d conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 9.2.6 ?a/d conversion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 9.3 ?a/d acquisition requirements? .
? 2010 microchip technology inc. preliminary ds41418a-page 83 pic16f707/pic16lf707 example 9-1: a/d conversion ;this code block configures the adc ;for polling, vdd reference, frc clock ;and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?01110000? ;adc frc clock, ;v dd reference movwf adcon1 ; banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansela ; bsf ansela,0 ;set ra0 to analog banksel adcon0 ; movlw b?00000001?;an0, on movwf adcon0 ; call sampletime ;acquisiton delay bsf adcon0,go ;start conversion btfsc adcon0,go ;is conversion done? goto $-1 ;no, test again banksel adres ; movf adres,w ;read result movwf result ;store in gpr space
pic16f707/pic16lf707 ds41418a-page 84 preliminary ? 2010 microchip technology inc. 9.2.7 adc register definitions the following registers are used to control the operation of the adc. register 9-1: adcon0: a/ d control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs<3:0>: analog channel select bits 0000 =an0 0001 =an1 0010 =an2 0011 =an3 0100 =an4 0101 =an5 0110 =an6 0111 =an7 1000 =an8 1001 =an9 1010 =an10 1011 =an11 1100 =an12 1101 =an13 1110 =reserved 1111 = fixed voltage reference (fv ref ) bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current
? 2010 microchip technology inc. preliminary ds41418a-page 85 pic16f707/pic16lf707 register 9-2: adcon1: a/ d control register 1 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ? adcs2 adcs1 adcs0 ? ? adref1 adref0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 011 =f rc (clock supplied from a dedicated rc oscillator) 100 =f osc /4 101 =f osc /16 110 =f osc /64 111 =f rc (clock supplied from a dedicated rc oscillator) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adref<1:0>: voltage reference configuration bits 0x =v ref is connected to v dd 10 =v ref is connected to external v ref (ra3/an3) 11 =v ref is connected to internal fixed voltage reference register 9-3: adres: adc result register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<7:0> : adc result register bits 8-bit conversion result.
pic16f707/pic16lf707 ds41418a-page 86 preliminary ? 2010 microchip technology inc. 9.3 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 9-3. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 9-3. the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 9-1 may be used. this equation assumes that 1/2 lsb error is used (256 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 9-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/511) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.001957) = 1.12 = s t acq 2s 1.12s 50c- 25c ?? 0.05s/c ?? ?? ++ = 4.42s = v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification.
? 2010 microchip technology inc. preliminary ds41418a-page 87 pic16f707/pic16lf707 figure 9-3: analog input model figure 9-4: adc transfer function c pin va rs anx 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 25.0 ?electrical specifications? . r ss = resistance of sampling switch ffh feh adc output code fdh fch 04h 03h 02h 01h 00h full-scale fbh 1 lsb ideal v ss zero-scale transition v ref transition 1 lsb ideal full-scale range analog input voltage
pic16f707/pic16lf707 ds41418a-page 88 preliminary ? 2010 microchip technology inc. table 9-2: summary of associated adc registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 adcon1 ? adcs2 adcs1 adcs0 ? ? adref1 adref0 -000 --00 -000 --00 ansela ansa7 ansa6 ansa5 ansa4 ansa3 ansa2 ansa1 ansa0 1111 1111 1111 1111 anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 ansele ? ? ? ? ? anse2 anse1 anse0 ---- -111 ---- -111 adres a/d result register byte xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 fvrcon fvrrdy fvren ? ? cdafvr1 cdafvr0 adfvr1 adfvr0 q000 0000 q000 0000 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 trisb trisb7 trisb6 trisb5 trisb4 tri sb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 trise ? ? ? ? trise3 trise2 trise1 trise0 ---- 1111 ---- 1111 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends on condition . shaded cells are not used for adc module.
? 2010 microchip technology inc. preliminary ds41418a-page 89 pic16f707/pic16lf707 10.0 fixed voltage reference the fixed voltage reference, or fvr, is a stable voltage reference independent of v dd with 1.024v, 2.048v or 4.096v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: ? adc input channel ? adc positive reference ? digital-to-analog converter (dac) ? capacitive sensing modules (csm) the fvr can be enabled by setting the fvren bit of the fvrcon register. 10.1 independent gain amplifiers the output of the fvr supplied to the adc and csm/dac modules is routed through the two independent programmable gain amplifiers. each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 9.0 ?analog-to-digital converter (adc) module? for additional information on selecting the appropriate input channel. the cdafvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the capacitive sensing and digital-to-analog converter modules. reference section 16.0 ?capacitive sensing module? and section 11.0 ?digital-to-analog converter (dac) module? for additional information. 10.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see section 25.0 ?electrical specifications? for the minimum delay requirement. figure 10-1: voltage reference block diagram adfvr<1:0> cdafvr<1:0> x 1 x 2 x 4 x 1 x 2 x 4 2 2 fvr buffer1 (to adc module) fvr buffer2 (to cap sense, dac) + _ fvren fvrrdy 1.024v fixed reference
pic16f707/pic16lf707 ds41418a-page 90 preliminary ? 2010 microchip technology inc. register 10-1: fvrcon: fixed voltage reference register r-q r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 fvrrdy (1) fvren ? ? cdafvr1 (2) cdafvr0 (2) adfvr1 (2) adfvr0 (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown q = value depends on condition bit 7 fvrrdy: fixed voltage reference ready flag bit (1) 0 = fixed voltage reference output is not active or stable 1 = fixed voltage reference output is ready for use bit 6 fvren: fixed voltage reference enable bit 0 = fixed voltage reference is disabled 1 = fixed voltage reference is enabled bit 5-4 reserved: read as ? 0 ?. maintain these bits clear bit 3-2 cdafvr<1:0>: cap sense and d/a converter fixed voltage reference selection bit (2) 00 = csm and d/a converter fixed voltage reference peripheral output is off. 01 = csm and d/a converter fixed voltage reference peripheral output is 1x (1.024v) 10 = csm and d/a converter fixed voltage reference peripheral output is 2x (2.048v) 11 = csm and d/a converter fixed voltage reference peripheral output is 4x (4.096v) bit 1-0 adfvr<1:0>: a/d converter fixed voltage reference selection bit (2) 00 = a/d converter fixed voltage reference peripheral output is off. 01 = a/d converter fixed voltage reference peripheral output is 1x (1.024v) 10 = a/d converter fixed voltage reference peripheral output is 2x (2.048v) 11 = a/d converter fixed voltage reference peripheral output is 4x (4.096v) note 1: fvrrdy is always ? 1 ? on pic16f707 devices. 2: fixed voltage reference output cannot exceed v dd . table 10-1: registers associated with voltage reference name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets fvrcon fvrrdy fvren reserved reserved cdafvr1 cdafvr0 adfvr1 adfvr0 q000 0000 q000 0000 legend: shaded cells are not used by t he voltage reference module.
? 2010 microchip technology inc. preliminary ds41418a-page 91 pic16f707/pic16lf707 11.0 digital-to-analog converter (dac) module the digital-to-analog converter supplies a variable voltage reference, ratiometric with v dd , with 32 selectable output levels. the output of the dac can be configured to supply a reference voltage to the following: ? dacout device pin ? capacitive sensing modules the digital-to-analog converter (dac) can be enabled by setting the dacen bit of the daccon0 register. 11.1 output voltage selection the dac has 32 voltage level ranges. the 32 levels are set with the dacr<4:0> bits of the daccon1 register. the dac output voltage is determined by the following equation: equation 11-1: 11.2 output clamped to v ss the dac output voltage can be set to v ss with no power consumption by setting the dacen bit of the daccon0 register to ? 0 ?. 11.3 output ratiometric to v dd the dac is v dd derived and therefore, the dac output changes with fluctuations in v dd . the tested absolute accuracy of the dac can be found in section 25.0 ?electrical specifications? . 11.4 voltage reference output the dac can be output to the device dacout pin by setting the dacoe bit of the daccon0 register to ? 1 ?. selecting the reference voltage for output on the dacout pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. reading the dacout pin when it has been configured for reference voltage output will always return a ? 0 ?. due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to dacout. example 11-1 shows an example buffering technique. 11.5 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the daccon0 register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 11.6 effects of a reset a device reset affects the following: ? voltage reference is disabled ? fixed voltage reference is disabled ? dac is removed from the dacout pin ? the dacr<4:0> range select bits are cleared v out v source v source ? ?? x dacr[4:0] 2 5 ----------------------------- ?? ?? ?? v source + = - if dacen = 1 if dacen = 0 & daclps = 1 & dacr[4:0] = 11111 v out v source = + if dacen = 0 & daclps = 0 & dacr[4:0] = 00000 v out v source = - v source + = v dd , v ref , or fvr buffer 2 v source - = v ss + -
pic16f707/pic16lf707 ds41418a-page 92 preliminary ? 2010 microchip technology inc. figure 11-1: digital-to-analog converter block diagram example 11-1: voltage reference output buffer example 16-to-1 mux dacr<4:0> r dacen v dd v ref dacpss[1:0] = 00 r r r r r r 32 steps dac fvr dacpss[1:0] = 01 dacpss[1:0] = 10 dacout pin dacoe daclps dacen daclps buffer 2 (to capacitive sensing module) r buffered dac output + ? dac module voltage reference output impedance r dacout pic16f707/ pic16lf707
? 2010 microchip technology inc. preliminary ds41418a-page 93 pic16f707/pic16lf707 register 11-1: daccon0: voltage reference control register 0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 u-0 dacen daclps dacoe ? dacpss1 dacpss0 ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 dacen: digital-to-analog converter enable bit 0 = digital-to-analog converter is disabled 1 = digital-to-analog converter is enabled bit 6 daclps: dac low-power voltage state select bit 0 =v dac = dac negative reference source selected 1 =v dac = dac positive reference source selected bit 5 dacoe: dac voltage output enable bit 0 = dac voltage level is output on the dacout pin 1 = dac voltage level is disconnected from the dacout pin bit 4 unimplemented: read as ? 0 ? bit 3-2 dacpss<1:0>: dac positive source select bits 00 =v dd 01 =v ref 10 = fvr buffer 2 output 11 = reserved, do not use bit 1-0 unimplemented: read as ? 0 ? register 11-2: daccon1: voltage reference control register 1 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? dacr4 dacr3 dacr2 dacr1 dacr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4-0 dacr<4:0>: dac voltage output select bits
pic16f707/pic16lf707 ds41418a-page 94 preliminary ? 2010 microchip technology inc. table 11-1: registers associated wi th the digital-to-analog converter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets fvrcon fvrrdy fvren reserved reserved cdafvr1 cdafvr0 adfvr1 adfvr0 q000 0000 q000 0000 daccon0 dacen daclps dacoe ? dacpss1 dacpss0 ? ? 000- 00-- 000- 00-- daccon1 ? ? ? dacr4 dacr3 dacr2 dacr1 dacr0 ---0 0000 ---0 0000 legend: ? = unimplemented locations, read as ?0?. shaded cells are not used by the dac module.
? 2010 microchip technology inc. preliminary ds41418a-page 95 pic16f707/pic16lf707 12.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (shared with watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow figure 12-1 is a block diagram of the timer0 module. figure 12-1: block diagram of the timer0/wdt prescaler t0cki tmr0se tmr0 wdt time-out ps<2:0> wdte data bus set flag bit tmr0if on overflow tmr0cs 0 1 0 1 0 1 8 8 8-bit prescaler 0 1 f osc /4 psa psa psa sync 2 t cy divide by 512 tmr1ge t1gss = 11 pin note 1: tmr0se, tmr0cs, psa, ps<2:0> are bits in the option register. 2: wdte bit is in configuration word 1. 3: t1gss and tmr1ge are in the t1gcon register.
pic16f707/pic16lf707 ds41418a-page 96 preliminary ? 2010 microchip technology inc. 12.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 12.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 12.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin. 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit of the option register to ? 1 ?. the rising or falling transition of the incrementing edge for either input source is determined by the tmr0se bit in the option register. 12.1.3 software programmable prescaler a single software programmable prescaler is available for use with either timer0 or the watchdog timer (wdt), but not both simultaneously. the prescaler assignment is controlled by the psa bit of the option register. to assign the prescaler to timer0, the psa bit must be cleared to a ? 0 ?. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be assigned to the wdt module. the prescaler is not readable or writable. when the prescaler is enabled or assigned to the timer0 module, all instructions writing to the tmr0 register will clear the prescaler. 12.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 12.1.5 using timer0 with an external clock when timer0 is in counter mode, the synchronization of the t0cki input and the timer0 register is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, the high and low periods of the external clock source must meet the timing requirements as shown in section 25.0 ?electrical specifications? . 12.1.6 timer enable operation of timer0 is always enabled and the module will operate according to the settings of the option register. 12.1.7 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. note: when the prescaler is assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep.
? 2010 microchip technology inc. preliminary ds41418a-page 97 pic16f707/pic16lf707 register 12-1: option_reg: option register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg tmr0cs tmr0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate table 12-1: summary of registers associated with timer0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x option_reg rbpu intedg tmr0cs tmr0se psa ps2 ps1 ps0 1111 1111 1111 1111 tmr0 timer0 module register xxxx xxxx uuuu uuuu trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by the timer0 module.
pic16f707/pic16lf707 ds41418a-page 98 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 99 pic16f707/pic16lf707 13.0 timer1/3 modules with gate control the timer1 and timer3 modules are 16-bit timers/ counters with the following features: ? 16-bit timer/counter register pair (tmrxh:tmrxl) ? programmable internal or external clock source ? 3-bit prescaler ? dedicated lp oscillator circuit (timer1 only) ? synchronous or asynchronous operation ? multiple timer1/3 gate (count enable) sources ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? time base for the capture/compare function (timer1 only) ? special event trigger with ccp (timer1 only) ? selectable gate source polarity ? gate toggle mode ? gate single-pulse mode ? gate value status ? gate event interrupt figure 13-1 is a block diagram of the timer1/3 modules.
pic16f707/pic16lf707 ds41418a-page 100 preliminary ? 2010 microchip technology inc. figure 13-1: timer1/timer3 block diagram tmrxh tmrxl t xs ync txckps<1:0> prescaler 1, 2, 4, 8 0 1 synchronized clock input 2 set flag bit tmrxif on overflow tmrx (2) tmrxon note 1: st buffer is high speed type when using txcki. 2: timer1/3 register increments on rising edge. 3: synchronize does not operate while in sleep. 4: timer1 gate source is timera. timer3 gate source is timerb. refer to table 13-1. 5: timer1 clock source is cpsaosc. timer3 clock source is cpsbosc. refer to table 13-1. 6: timer3 does not have a t3osc circuit. there is no t3oscen bit. timer3 can operate from t1osc. txg t1osc f osc internal clock t1oso/t1cki t1osi t1oscen 1 0 txcki tmrxcs<1:0> (1) synchronize (3) det sleep input tmrxge 0 1 00 01 10 11 from timera/b from timer2 txgpol d q ck q 0 1 txgval txgtm single pulse acq. control txgspm txggo/done txgss<1:0> en out 11 10 00 00 f osc /4 internal clock from wdt overflow match pr2 overflow (4) r d en q q1 rd txgcon data bus det interrupt tmrxgif set txclk f osc /2 internal clock d en q txg_in (6) cap. sense (5) oscillator a/b table 13-1: cpsosc/timer association period measurement cap sense oscillator divider timer (gate source) timer1 cps a timera timer3 cps b timerb
? 2010 microchip technology inc. preliminary ds41418a-page 101 pic16f707/pic16lf707 13.1 timer1/3 operation the timer1 and timer3 modules are 16-bit increment- ing counters which are accessed through the tmrxh:tmrxl register pa ir. writes to tmrxh or tmrxl directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source. timer1/3 is enabled by configuring the tmrxon and tmrxge bits in the txcon and txgcon registers, respectively. table 13-2 displays the timer1/3 enable selections. 13.2 clock source selection the tmrxcs<1:0> bits of the txcon register and the t1oscen bit of the t1con register are used to select the clock source for timer1/3. table 13-3 displays the clock source selections. 13.2.1 internal clock source when the internal clock source is selected, the tmrxh:tmrxl register pair will increment on multiples of f osc as determined by the timer1/3 prescaler. 13.2.2 external clock source when the external clock source is selected, the timer1/3 modules may work as a timer or a counter. when enabled to count, timer1/3 is incremented on the rising edge of the external clock input txcki or a capacitive sensing oscillator signal. either of these external clock sources can be synchronized to the microcontroller system clock or they can be run asynchronously. if set for the capacitive sensing oscillator signal, timer1 will use the cps a signal and timer3 will use the cps b signal (see table 13-1). when used as a timer with a clock oscillator, an external 32.768 khz crystal can be used in conjunction with the dedicated internal oscillator circuit. only one dedicated internal oscillator circuit is available. see section 13.4 ?timer1/3 oscillator? for more information. table 13-2: timer1/3 enable selections tmrxon tmrxge timer1/3 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: ? timer1/3 enabled after por reset ? write to tmrxh or tmrxl ? timer1/3 is disabled ? timer1/3 is disabled (tmrxon = 0 ) when txcki is high, then timer1/3 is enabled (tmrxon= 1 ) when txcki is low. table 13-3: clock source selections tmrxcs1 tmrxcs0 t1oscen timer1 clock source timer3 clock source 01x system clock (f osc ) system clock (f osc ) 00x instruction clock (f osc /4) instruction clock (f osc /4) 11x capacitive sensing a oscillator capacitive sensing b oscillator 100 external clocking on t1cki pin e xternal clocking on t3cki pin 101 oscillator circuit on t1osi/ t1oso pins oscillator circuit on t1osi/ t1oso pins
pic16f707/pic16lf707 ds41418a-page 102 preliminary ? 2010 microchip technology inc. 13.3 timer1/3 prescaler timer1 and timer3 have four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the txckps bits of the txcon register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmrxh or tmrxl. 13.4 timer1/3 oscillator a dedicated low-power 32.768 khz oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). this internal circuit is to be used in conjunction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the t1oscen bit of the t1con register. the oscillator can provide a clock source to timer1 and/or timer3. the oscillator will continue to run during sleep. 13.5 timer1/3 operation in asynchronous counter mode if control bit t xs ync of the txcon register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if external clock source is selected, then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 13.5.1 ?reading and writing timer1/3 in asynchronous counter mode? ). 13.5.1 reading and writing timer1/3 in asynchronous counter mode reading tmrxh or tmrxl while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmrxh:tmrxl register pair. 13.6 timer1/3 gate timer1/3 can be configured to count freely or the count can be enabled and disabled using timer1/3 gate circuitry. this is also referred to as timer1/3 gate count enable. timer1/3 gate can also be driven by multiple selectable sources. 13.6.1 timer1/3 gate count enable the timer1/3 gate is enabled by setting the tmrxge bit of the txgcon register. the polarity of the timer1/3 gate is configured using the txgpol bit of the txgcon register. when timer1/3 gate (txg) input is active, timer1/3 will increment on the rising edge of the timer1/3 clock source. when timer1/3 gate input is inactive, no incre- menting will occur and timer1/3 will hold the current count. see figure 13-3 for timing details. 13.6.2 timer1/3 gate source selection the timer1/3 gate source can be selected from one of four different sources. source selection is controlled by the txgss bits of the txgcon register. the polarity for each available source is also selectable. polarity selection is controlled by the txgpol bit of the txgcon register. note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to enabling timer1/3. table 13-4: timer1/3 gate enable selections txclk txgpol txg timer1/3 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts
? 2010 microchip technology inc. preliminary ds41418a-page 103 pic16f707/pic16lf707 13.6.3 txg pin gate operation the txg pin is one source for timer1/3 gate control. it can be used to supply an external source to the timer1/3 gate circuitry. timer1 gate can be configured for the t1g pin and timer3 gate can be configured for the t3g pin. 13.6.4 timera/b overflow gate operation when timera/b increments from ffh to 00h a low-to- high pulse will automatically be generated and internally supplied to the timer1/3 gate circuitry. timer1 gate can be configured for timera overflow and timer3 gate can be configured for timerb overflow. 13.6.5 timer2 match gate operation the tmr2 register will increment until it matches the value in the pr2 register. on the very next increment cycle, tmr2 will be reset to 00h. when this reset occurs, a low-to-high pulse will automatically be gener- ated and internally supplied to the timer1/3 gate cir- cuitry. both timer1 gate and timer3 gate can be configured for the timer2 match. 13.6.6 watchdog overflow gate operation the watchdog timer oscillator, prescaler and counter will be automatically turned on when tmrxge = 1 and txgss selects the wdt as a gate source for timer1/3 (txgss = 11 ). tmrxon does not factor into the oscil- lator, prescaler and counter enable. see table 13-6. both timer1 gate and timer3 gate can be configured for watchdog overflow. the psa and ps bits of the option register still control what time-out interval is selected. changing the prescaler during operation may result in a spurious capture. enabling the watchdog timer oscillator does not automatically enable a watchdog reset or wake-up from sleep upon counter overflow. as the gate signal coming from the wdt counter will generate different pulse widths, depending on if the wdt is enabled, when the clrwdt instruction is exe- cuted, and so on, toggle mode must be used. a spe- cific sequence is required to put the device into the correct state to capture the next wdt counter interval. table 13-5: timer1/3 gate sources txgss timer1 gate source timer3 gate source 00 timer1 gate pin timer3 gate pin 01 overflow of timera (tmra increments from ffh to 00h) overflow of timerb (tmrb increments from ffh to 00h) 10 timer2 match pr2 (tmr2 increments to match pr2) timer2 match pr2 (tmr2 increments to match pr2) 11 count enabled by wdt overflow (watchdog time-out interval expired) count enabled by wdt overflow (watchdog time-out interval expired) note: when using the wdt as a gate source for timer1/3, operations that clear the watchdog timer ( clrwdt , sleep instructions) will affect the time interval being measured for capacitive sensing. this includes waking from sleep. all other interrupts that might wake the device from sleep should be disabled to prevent them from disturbing the measurement period. table 13-6: wdt/timer1/3 gate interraction wdte tmrxge = 1 and txgss = 11 wdt oscillator enable wdt reset wake-up wdt available for txg source 1 ny yyn 1 yy yyy 0 yynny 0 nn nnn
pic16f707/pic16lf707 ds41418a-page 104 preliminary ? 2010 microchip technology inc. 13.6.7 timer1/3 gate toggle mode when timer1/3 gate toggle mode is enabled, it is possible to measure the full-cycle length of a timer1/3 gate signal, as opposed to the duration of a single level pulse. the timer1/3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. see figure 13-4 for timing details. timer1/3 gate toggle mode is enabled by setting the txgtm bit of the txgcon register. when the txgtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 13.6.8 timer1/3 gate single-pulse mode when timer1/3 gate single-pulse mode is enabled, it is possible to capture a single pulse gate event. timer1/3 gate single-pulse mode is first enabled by setting the txgspm bit in the txgcon register. next, the txggo/done bit in the txgcon register must be set. the timer1/3 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the txggo/done bit will automatically be cleared. no other gate events will be allowed to incre- ment timer1/3 until the txggo/done bit is once again set in software. clearing the txgspm bit of the txgcon register will also clear the txggo/done bit. see figure 13-5 for timing details. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1/3 gate source to be measured. see figure 13-6 for timing details. 13.6.9 timer1/3 gate value status when timer1/3 gate value status is utilized, it is possible to read the most current level of the gate control value. the value is stored in the txgval bit in the txgcon register. the txgval bit is valid even when the timer1/3 gate is not enabled (tmrxge bit is cleared). 13.6.10 timer1/3 gate event interrupt when timer1/3 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. when the falling edge of txgval occurs, the tmrxgif flag bit in the pirx register will be set. if the tmrxgie bit in the piex register is set, then an interrupt will be recognized. see table 13-7 for interrupt bit locations. the tmrxgif flag bit operates even when the timer1/3 gate is not enabled (tmrxge bit is cleared). 13.7 timer1/3 interrupt the timer1/3 register pair (tmrxh:tmrxl) increments to ffffh and rolls over to 0000h. when timer1/3 rolls over, the timer1/3 interrupt flag bit of the pirx register is set. see table 13-7 for interrupt bit locations. to enable the interrupt on rollover, you must set these bits: ? tmrxon bit of the txcon register ? tmrxie bit of the piex register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmrxif bit in the interrupt service routine. note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation. table 13-7: timer1/3 interrupt bit locations timer1 timer3 interrupt flag tmr1if bit in pir1 register tmr3if bit in pir2 register interrupt enable tmr1ie bit in pie1 register tmr3ie bit in pie2 register gate interrupt flag tmr1gif bit in pir1 register tmr3gif bit in pir2 register gate interrupt enable tmr1gie bit in pie1 register tmr3gie bit in pie2 register note: the tmrxh:tmrxl register pair and the tmrxif bit should be cleared before enabling interrupts.
? 2010 microchip technology inc. preliminary ds41418a-page 105 pic16f707/pic16lf707 13.8 timer1/3 operation during sleep timer1/3 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmrxon bit of the txcon register must be set ? tmrxie bit of the piex register must be set ? peie bit of the intcon register must be set ? txsync bit of the txcon register must be set ? tmrxcs bits of the txcon register must be configured ? t1oscen bit of the t1con register must be configured ? tmrxgie bit of the txgcon register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine (0004h). 13.9 ccp capture/compare time base (timer1 only) the ccp module uses the tmr1h:tmr1l register pair as the time base when operating in capture or compare mode. in capture mode, the value in the tmr1h:tmr1l register pair is copied into the ccpr1h:ccpr1l register pair on a configured event. in compare mode, an event is triggered when the value ccpr1h:ccpr1l register pair matches the value in the tmr1h:tmr1l register pair. this event can be a special event trigger. for more information, see section 17.0 ?capture/ compare/pwm (ccp) module?. 13.10 ccp special event trigger (timer1 only) when the ccp is configured to trigger a special event, the trigger will clear the tmr1h:tmr1l register pair. this special event does not cause a timer1 interrupt. the ccp module may still be configured to generate a ccp interrupt. in this mode of operation, the ccpr1h:ccpr1l register pair becomes the period register for timer1. timer1 should be synchronized to the f osc /4 to utilize the special event trigger. asynchronous operation of timer1 can cause a special event trigger to be missed. in the event that a write to tmr1h or tmr1l coincides with a special event trigger from the ccp, the write will take precedence. for more information, see section 17.2.4 ?special event trigger?. figure 13-2: timer1/timer3 incrementing edge txcki = 1 when tmr1/3 enabled txcki = 0 when tmr1/3 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
pic16f707/pic16lf707 ds41418a-page 106 preliminary ? 2010 microchip technology inc. figure 13-3: timer1/timer3 gate count enable mode figure 13-4: timer1/timer3 gate toggle mode tmrxge txgpol txg_in txcki txgval timer1/3 n n + 1 n + 2 n + 3 n + 4 tmrxge txgpol txgtm txg_in txcki txgval timer1/3 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8
? 2010 microchip technology inc. preliminary ds41418a-page 107 pic16f707/pic16lf707 figure 13-5: timer1/timer3 gate single-pulse mode tmrxge txgpol txg_in txcki txgval timer1/3 n n + 1 n + 2 txgspm txggo/ done set by software cleared by hardware on falling edge of txgval set by hardware on falling edge of txgval cleared by software cleared by software tmrxgif counting enabled on rising edge of txg
pic16f707/pic16lf707 ds41418a-page 108 preliminary ? 2010 microchip technology inc. figure 13-6: timer1/timer3 gate sing le-pulse and toggle combined mode tmrxge txgpol txg_in txcki txgval timer1/3 nn + 1 n + 2 txgspm txggo/ done set by software cleared by hardware on falling edge of txgval set by hardware on falling edge of txgval cleared by software cleared by software tmrxgif txgtm counting enabled on rising edge of txg n + 4 n + 3
? 2010 microchip technology inc. preliminary ds41418a-page 109 pic16f707/pic16lf707 13.11 timer1/3 control register the timer1/3 control register (txcon), shown in register 13-1, is used to control timer1/3 and select the various features of the timer1/3 module. register 13-1: txcon: time r1/timer3 control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 tmrxcs1 tmrxcs0 txckps1 txckps0 t1oscen (1) txsync ?tmrxon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 tmrxcs<1:0>: timerx clock source select bits 11 = timerx clock source is capacitive sensing oscillator (cpsxosc) 10 = timerx clock source is pin or oscillator: if t 1o scen = 0 : external clock from txcki pin (on the rising edge) if t 1o scen = 1 : crystal oscillator on t1osi/t1oso pins 01 = timerx clock source is system clock (f osc ) 00 = timerx clock source is instruction clock (f osc /4) bit 5-4 txckps<1:0>: timerx input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit (1) 1 = dedicated timer1/3 oscillator circuit enabled 0 = dedicated timer1/3 oscillator circuit disabled bit 2 tx sync : timerx external clock input synchronization control bit if tmrxcs<1:0> = 1x 1 = do not synchronize external clock input 0 = synchronize external clock input with system clock (f osc ) if tmrxcs<1:0> = 0x this bit is ignored. timerx uses the internal clock when tmr1cs<1:0> = 0x . bit 1 unimplemented: read as ? 0 ? bit 0 tmrxon: timerx on bit 1 = enables timerx 0 = stops timerx clears timerx gate flip-flop
pic16f707/pic16lf707 ds41418a-page 110 preliminary ? 2010 microchip technology inc. register 13-2: txgcon: timer1/t imer3 gate control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 r/w-0/0 r/w-0/0 tmrxge txgpol txgtm txgspm txggo/ done txgval txgss1 txgss0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 tmrxge: timerx gate enable bit if tmrxon = 0 : this bit is ignored. if tmrxon = 1 : 1 = timerx counting is controlled by the timerx gate function 0 = timerx counts regardless of timerx gate function bit 6 txgpol: timerx gate polarity bit 1 = timerx gate is active-high (timerx counts when gate is high) 0 = timerx gate is active-low (timerx counts when gate is low) bit 5 txgtm: timerx gate toggle mode bit 1 = timerx gate toggle mode is enabled 0 = timerx gate toggle mode is disabled and toggle flip-flop is cleared timerx gate flip-flop toggles on every rising edge. bit 4 txgspm: timerx gate single-pulse mode bit 1 = timerx gate single-pulse mode is enabled and is controlling timerx gate 0 = timerx gate single-pulse mode is disabled bit 3 txggo/done : timerx gate single-pulse acquisition status bit 1 = timerx gate single-pulse acquisition is ready, waiting for an edge 0 = timerx gate single-pulse acquisition has completed or has not been started this bit is automatically cleared when t1gspm is cleared. bit 2 txgval: timerx gate current state bit indicates the current state of the timerx gate that could be provided to tmrxh:tmrxl. unaffected by timerx gate enable (tmrxge). bit 1-0 txgss<1:0>: timerx gate source select bits 00 = timerx gate pin 01 = timera/b overflow output 10 = tmr2 match pr2 output 11 = watchdog timer scaler overflow watchdog timer oscillator is turned on if tmrxge = 1 , regardless of the state of tmr1on.
? 2010 microchip technology inc. preliminary ds41418a-page 111 pic16f707/pic16lf707 14.0 timera/b modules timera and timerb are two more timer0-type modules. timers a and b are available as general- purpose timers/counters, and are closely integrated with the capacitive sensing modules. the timera/b modules incorporate the following features: ? 8-bit timer/counter register (tmrx) ? 8-bit prescaler ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow ? tmra can be used to gate timer1 ? tmrb can be used to gate timer3 figure 14-1 is a block diagram of the timera/timerb modules. figure 14-1: block diagram of the timera/timerb prescaler txcki tmrxse pin tmrx tmrxps<2:0> data bus set flag bit tmrxif on overflow tmrxcs note 1: txxcs is in the cpsxcon0 register. 0 1 0 1 8 8 8-bit prescaler f osc /4 tmrxpsa sync 2 tcy overflow to timer1/3 1 0 txxcs from cpsxosc
pic16f707/pic16lf707 ds41418a-page 112 preliminary ? 2010 microchip technology inc. 14.1 timera/b operation the timera/b modules can be used as either 8-bit tim- ers or 8-bit counters. additionally, the modules can also be used to set timer1?s/timer3?s period of measure- ment for the capacitive sensing modules via timer1?s or timer3?s gate feature. 14.1.1 8-bit timer mode the timera/b modules will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmrxcs bit of the txcon registers. when tmrx is written, the increment is inhibited for two instruction cycles immediately following the write. 14.1.2 8-bit counter mode in 8-bit counter mode, the timera/b modules will increment on every rising or falling edge of the txcki pin or the capacitive sensing oscillator (cpsxosc) signal. 8-bit counter mode using the txcki pin is selected by setting the tmrxcs bit of the txcon register to ? 1 ? and resetting the txxcs bit in the cpsxcon0 register to ? 0 ?. 8-bit counter mode using the capacitive sensing oscillator (cpsxosc) signal is selected by setting the tmrxcs bit in the txcon register to ? 1 ? and setting the txxcs bit in the cpsxcon0 register to ? 1 ?. the rising or falling transition of the incrementing edge for either input source is determined by the tmrxse bit in the txcon register. 14.1.3 software programmable prescaler for timera/b modules, the software programmable prescaler is exclusive to the timer. the prescaler is enabled by clearing the tmrxpsa bit of the txcon register. there are 8 prescaler options for timera/b modules ranging from 1:2 to 1:256. the prescale values are selectable via the tmrxps<2:0> bits of the txcon register for timera/b. in order to have a 1:1 prescaler value for the timera/b modules, the prescaler must be disabled. the prescaler is not readable or writable. when the prescaler is enabled or assigned to the timer module, all instructions writing to the tmrx register will clear the prescaler. enabling the timera/b modules also clears the prescaler. 14.1.4 timera/b interrupt timera/b will generate an interrupt when the corresponding tmr register overflows from ffh to 00h. the tmrxif interrupt flag bit of the pir2 register is set every time the tmrx register overflows. these interrupt flag bits are set regardless of whether or not the relative timer interrupt is enabled. the interrupt flag bits can only be cleared in software. the timera/b interrupt enable bits are the tmrxie in the pie2 register. 14.1.5 using timera/b with an external clock when timera/b is in counter mode, the synchronization of the txcki input and the tmrx register is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, the high and low periods of the external clock source must meet the timing requirements as shown in section 25.0 ?electrical specifications? . 14.1.6 timer enable operation of timera/b is enabled by setting the tmrxon bit of the txcon register. when the module is disabled, the value in the tmrx register is maintained. enabling the tmrx module will reset the prescaler used by the counter. 14.1.7 operation during sleep timera and timerb cannot operate while the processor is in sleep mode. the contents of the tmrx registers will remain unchanged while the processor is in sleep mode. table 14-1: cpsosc/timer association cap sense oscillator divider timer period measurement cps a timera timer1 cps b timerb timer3 note: the value written to the tmrx register can be adjusted, in order to account for the two instruction cycle delay when tmrx is written. note: timera/b interrupts cannot wake the processor from sleep since the timer is frozen during sleep.
? 2010 microchip technology inc. preliminary ds41418a-page 113 pic16f707/pic16lf707 register 14-1: txcon: time ra/timerb control register r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmrxon ? tmrxcs tmrxse tmrx ps a tmrxps2 tmrxps1 tmrxps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmrxon: timera/timerb on/off control bit 1 = timerx is enabled 0 = timerx is disabled bit 6 unimplemented: read as ? 0 ? bit 5 tmrxcs: tmrx clock source select bit 1 = transition on txcki pin or cpsxosc signal 0 = internal instruction cycle clock (f osc /4) bit 4 tmrxse: tmrx source edge select bit 1 = increment on high-to-low transition on txcki pin 0 = increment on low-to-high transition on txcki pin bit 3 tmrx psa : prescaler assignment bit 1 = prescaler is disabled. timer clock input bypasses prescaler. 0 = prescaler is enabled. timer clock input comes from the prescaler output. bit 2-0 tmrxps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value tmrx rate table 14-2: summary of registers associated with timera/b name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 00-- 0000 00-- 0000 cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 pie2 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie 0000 ---0 0000 ---0 pir2 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if 0000 ---0 0000 ---0 tacon tmraon ? tacs tase tapsa taps2 taps1 taps0 0-00 0000 0-00 0000 tbcon tmrbon ? tbcs tbse tbpsa tbps2 tbps1 tbps0 0-00 0000 0-00 0000 tmra timera module register 0000 0000 0000 0000 tmrb timerb module register 0000 0000 0000 0000 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by the timera/b modules.
pic16f707/pic16lf707 ds41418a-page 114 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 115 pic16f707/pic16lf707 15.0 timer2 module the timer2 module is an 8-bit timer with the following features: ? 8-bit timer register (tmr2) ? 8-bit period register (pr2) ? interrupt on tmr2 match with pr2 ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) see figure 15-1 for a block diagram of timer2. 15.1 timer2 operation the clock input to the timer2 module is the system instruction clock (f osc /4). the clock is fed into the timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. the output of the prescaler is then used to increment the tmr2 register. the values of tmr2 and pr2 are constantly compared to determine when they match. tmr2 will increment from 00h until it matches the value in pr2. when a match occurs, two things happen: ? tmr2 is reset to 00h on the next increment cycle. ? the timer2 postscaler is incremented. the match output of the timer2/pr2 comparator is then fed into the timer2 postscaler. the postscaler has postscale options of 1:1 to 1:16 inclusive. the output of the timer2 postscaler is used to set the tmr2if interrupt flag bit in the pir1 register. the tmr2 and pr2 registers are both fully readable and writable. on any reset, the tmr2 register is set to 00h and the pr2 register is set to ffh. timer2 is turned on by setting the tmr2on bit in the t2con register to a ? 1 ?. timer2 is turned off by clearing the tmr2on bit to a ? 0 ?. the timer2 prescaler is controlled by the t2ckps bits in the t2con register. the timer2 postscaler is controlled by the toutps bits in the t2con register. the prescaler and postscaler counters are cleared when: ? a write to tmr2 occurs. ? a write to t2con occurs. ? any device reset occurs (power-on reset, mclr reset, watchdog timer reset, or brown-out reset). figure 15-1: timer2 block diagram note: tmr2 is not cleared when t2con is written. comparator tmr2 sets flag tmr2 output reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if toutps<3:0> t2ckps<1:0>
pic16f707/pic16lf707 ds41418a-page 116 preliminary ? 2010 microchip technology inc. register 15-1: t2con: ti mer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps<3:0>: timer2 output postscaler select bits 0000 = 1:1 postscaler 0001 = 1:2 postscaler 0010 = 1:3 postscaler 0011 = 1:4 postscaler 0100 = 1:5 postscaler 0101 = 1:6 postscaler 0110 = 1:7 postscaler 0111 = 1:8 postscaler 1000 = 1:9 postscaler 1001 = 1:10 postscaler 1010 = 1:11 postscaler 1011 = 1:12 postscaler 1100 = 1:13 postscaler 1101 = 1:14 postscaler 1110 = 1:15 postscaler 1111 = 1:16 postscaler bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 =prescaler is 1 01 =prescaler is 4 1x = prescaler is 16 table 15-1: summary of registers associated with timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 tmr2 holding register for the 8-bit tmr2 register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as ? 0 ?. shaded cells are not used for timer2 module.
? 2010 microchip technology inc. preliminary ds41418a-page 117 pic16f707/pic16lf707 16.0 capacitive sensing module the capacitive sensing modules (csm) allow for an interaction with an end user without a mechanical interface. in a typical application, the capacitive sensing module is attached to a pad on a printed circuit board (pcb), which is electrically isolated from the end user. when the end user places their finger over the pcb pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module. the capacitive sensing module requires software and at least one timer resource to determine the change in frequency. key features of this module include: ? analog mux for monitoring multiple inputs ? capacitive sensing oscillator ? multiple power modes ? high power range with variable voltage references ? multiple timer resources ? software control ? operation during sleep ? acquire two samples simultaneously (when using both csm modules) two identical capacitive sensing modules are implemented on the pic16f707/pic16lf707. the modules are named cpsa and cpsb. the timer module integration for both capacitive sensing modules is shown in table 16-1. a block diagram of the capacitive sensing module is shown in figure 16-1 and figure 16-2. table 16-1: cpsosc timer usage cap sense oscillator mode frequency measurement duration control cap sense oscillator a timera/software timera software timer1/software timer1 software timer1/timera timer1 timera cap sense oscillator b timerb/software timerb software timer3/software timer3 software timer3/timerb timer3 timerb
pic16f707/pic16lf707 ds41418a-page 118 preliminary ? 2010 microchip technology inc. figure 16-1: capacitive sensing block diagram tmrxcs cpsx0 cpsx1 cpsx2 cpsx3 cpsx4 cpsx5 cpsx6 cpsx7 cpsx8 cpsx9 cpsx10 cpsxch<3:0> capacitive sensing oscillator cpsxrng<1:0> cpsxrm tmrx 0 1 set tmrxif overflow txxcs 0 1 txcki tmrxcs<1:0> t1osc/ txcki tmrxh:tmrxl en txgss<1:0> timer1/3 gate control logic txg cpsxout cpsx11 cpsx12 cpsx13 cpsx14 cpsx15 cpsxclk note 1: if cpsxon = 0 , disabling capacitive sensing, no channel is selected. f osc /4 f osc f osc /4 timera/b module timer1/3 module cpsxon (1) cpsxon 0 1 0 1 ref- ref+ dac fvr int. ref. cpsxosc watchdog timer module lp wdt osc wdt scaler overflow wdt event ps<2:0> timer2 module tmr2 overflow postscaler set tmr2if
? 2010 microchip technology inc. preliminary ds41418a-page 119 pic16f707/pic16lf707 figure 16-2: capacitive sensing oscillator block diagram 0 1 v dd cpsxclk oscillator module cpsx sq r + - + - note 1: module enable and power mode selections are not shown. 2: comparators remain active in noise detection mode. (2) (1) (1) (2) 0 1 internal references fvr (3) dac (3) cpsxrm analog pin ref- ref+
pic16f707/pic16lf707 ds41418a-page 120 preliminary ? 2010 microchip technology inc. 16.1 analog mux each capacitive sensing module can monitor up to 16 inputs, providing 32 capacitive sensing inputs in total. the capacitive sensing inputs are defined as cpsa<15:0> for capacitive sensing module a, and cpsb<15:0> for capacitive sensing module b. to determine if a frequency change has occurred the use must: ? select the appropriate cps pin by setting the cpsxch<3:0> bits of the cpsxcon1 register. ? set the corresponding ansel bit. ? set the corresponding tris bit. ? run the software algorithm. selection of the cpsx pin while the module is enabled will cause the capacitive sensing oscillator to be on the cpsx pin. failure to set the corresponding ansel and tris bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. 16.2 capacitive sensing oscillator the capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. the cpsxout bit of the cpsxcon0 register shows the status of the capacitive sensing oscillator, whether it is sinking or sourcing current. the oscillator is designed to drive a capacitive load (single pcb pad) and at the same time, be a clock source to either timera/b or timer1/3. the oscillator has three different current settings as defined by cpsxrng<1:0> of the cpsxcon0 register. the different current settings for the oscillator serve two purposes: ? maximize the number of counts in a timer for a fixed time base. ? maximize the count differential in the timer during a change in frequency. 16.3 voltage references the capacitive sensing oscillator uses voltage references to provide two voltage thresholds for oscillation. the upper voltage threshold is referred to as ref+ and the lower voltage threshold is referred to as ref-. the user can elect to use fixed voltage references, which are internal to the capacitive sensing oscillator, or variable voltage references, which are supplied by the fixed voltage reference (fvr) module and the digital-to-analog converter (dac) module. when the fixed voltage references are used, the v ss voltage determines the lower threshold level (ref-) and the v dd voltage determines the upper threshold level (ref+). when the variable voltage references are used, the dac voltage determines the lower threshold level (ref-) and the fvr voltage determines the upper threshold level (ref+). an advantage of using these ref- erence sources is that oscillation frequency remains constant with changes in v dd . different oscillation frequencies can be obtained through the use of these variable voltage references. the more the upper voltage reference level is lowered and the more the lower voltage reference level is raised, the higher the capacitive sensing oscillator frequency becomes. selection between the voltage references is controlled by the cpsxrm bit of the cpsxcon0 register. setting this bit selects the variable voltage references and clearing this bit selects the fixed voltage references. please see section 10.0 ?fixed voltage reference? and section 11.0 ?digital-to-analog converter (dac) module? for more information on configuring the variable voltage levels.
? 2010 microchip technology inc. preliminary ds41418a-page 121 pic16f707/pic16lf707 16.4 power modes the capacitive sensing oscillator can operate in one of seven different power modes. the power modes are separated into two ranges; the low range and the high range. when the oscillator's low range is selected, the fixed internal voltage references of the capacitive sensing oscillator are being used. when the oscillator's high range is selected, the variable voltage references supplied by the fvr and dac modules are being used. selection between the voltage references is controlled by the cpsxrm bit of the cpsxcon0 register. see section 16.3 ?voltage references? for more information. within each range there are three distinct power modes; low, medium and high. current consumption is dependent upon the range and mode selected. selecting power modes within each range is accom- plished by configuring the cpsxrng <1:0> bits in the cpsxcon0 register. see table 16-2 for proper power mode selection. the remaining mode is a noise detection mode that resides within the high range. the noise detection mode is unique in that it disables the sinking and sourc- ing of current on the analog pin but leaves the rest of the oscillator circuitry active. this reduces the oscilla- tion frequency on the analog pin to zero and also greatly reduces the current consumed by the oscillator module. when noise is introduced onto the pin, the oscillator is driven at the frequency determined by the noise. this produces a detectable signal at the comparator output, indicating the presence of activity on the pin. figure 16-2 shows a more detailed drawing of the current sources and comparators associated with the oscillator. 16.5 timer resources to measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. for the period of the fixed time base, the capacitive sensing oscillator is used to clock either timera/b or timer1/3 (for cpsa/b, respectively). the frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 16.6 fixed time base to measure the frequency of the capacitive sensing oscillator, a fixed time base is required. any timer resource or software loop can be used to establish the fixed time base. it is up to the end user to determine the method in which the fixed time base is generated. table 16-2: power mode selection cpsxrm range cpsxrng<1:0> mode nominal current (1) 0 low 00 off 0.0 a 01 low 0.1 a 10 medium 1.2 a 11 high 18 a 1 high 00 noise detection 0.0 a 01 low 9 a 10 medium 30 a 11 high 100 a note: see section 25.0 ?electrical specifications? for more information. note: the fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking.
pic16f707/pic16lf707 ds41418a-page 122 preliminary ? 2010 microchip technology inc. 16.6.1 timera/b to select timera/b as the timer resource for the capacitive sensing module: ? set the taxcs/tbxcs bit of the cpsacon0/ cpsbcon0 register. ? clear the tmracs/tmrbcs bit of the tacon/ tbcon register. when timera/b is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for timera/b. refer to section 14.0 ?timera/b mod- ules? for additional information. 16.6.2 timer1/3 to select timer1/3 as the timer resource for the capacitive sensing module, set the tmrxcs<1:0> of the txcon register to ? 11 ?. when timer1/3 is chosen as the timer resource, the capacitive sensing oscilla- tor will be the clock source for timer1/3. because the timer1/3 module has a gate control, developing a time base for the frequency measurement can be simplified by using the timera/b overflow flag. it is recommend that the timera/b overflow flag, in conjunction with the toggle mode of the timer1/3 gate, be used to develop the fixed time base required by the software portion of the capacitive sensing module. refer to section 13.11 ?timer1/3 control register ? for additional information. 16.7 software control the software portion of the capacitive sensing module is required to determine the change in frequency of the capacitive sensing oscillator. this is accomplished by the following: ? setting a fixed time base to acquire counts on timera/b or timer1/3. ? establishing the nominal frequency for the capacitive sensing oscillator. ? establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load. ? set the frequency threshold. 16.7.1 nominal frequency (no capacitive load) to determine the nominal frequency of the capacitive sensing oscillator: ? remove any extra capacitive load on the selected cpsx pin. ? at the start of the fixed time base, clear the timer resource. ? at the end of the fixed time base, save the value in the timer resource. the value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. the frequency of the capacitive sensing oscillator is equal to the number of counts on the timer divided by the period of the fixed time base. 16.7.2 reduced frequency (additional capacitive load) the extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. to determine the reduced frequency of the capacitive sensing oscillator: ? add a typical capacitive load on the selected cpsx pin. ? use the same fixed time base as the nominal frequency measurement. ? at the start of the fixed time base, clear the timer resource. ? at the end of the fixed time base, save the value in the timer resource. the value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. the frequency of the capacitive sensing oscillator is equal to the number of counts on the timer divided by the period of the fixed time base. this frequency should be less than the value obtained during the nominal frequency measurement. table 16-3: timer1/3 enable function tmrxon tmrxge timerx operation 00 off 01 off 10 on 11 count enabled by input
? 2010 microchip technology inc. preliminary ds41418a-page 123 pic16f707/pic16lf707 16.7.3 frequency threshold the frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. refer to application note an1103, ? software handling for capacitive sensing ? (ds01103) for more detailed information on the software required for capacitive sensing module. 16.8 operation during sleep the capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in sleep. in order for the software to determine if a frequency change has occurred, the part must be awake. however, the part does not have to be awake when the timer resource is acquiring counts. note: for more information on general capacitive sensing refer to application notes: ? an1101, ?introduction to capacitive sensing? (ds01101) ? an1102, ?layout and physical design guidelines for capacitive sensing? (ds01102). note: timera/b does not operate when in sleep, and therefore cannot be used for capacitive sense measurements in sleep.
pic16f707/pic16lf707 ds41418a-page 124 preliminary ? 2010 microchip technology inc. register 16-1: cpsxcon0: capacitiv e sensing control register 0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 r-0/0 r/w-0/0 cpsxon cpsxrm ? ? cpsxrng1 cpsxrng0 cpsxout txxcs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 cpsxon: capacitive sensing module enable bit 1 = capacitive sensing module is enabled 0 = capacitive sensing module is disabled bit 6 cpsxrm: capacitive sensing reference mode bit 1 = capacitive sensing module is in high range. dac and fvr provide oscillator voltage references. 0 = capacitive sensing module is in low range. internal oscillator voltage references are used. bit 5-4 unimplemented: read as ? 0 ? bit 3-2 cpsxrng<1:0>: capacitive sensing current range bits if cpsxrm = 0 (low range): 11 = oscillator is in high range: charge/discharge current is nominally 18 a. 10 = oscillator is in medium range. charge/discharge current is nominally 1.2 a. 01 = oscillator is in low range. charge/discharge current is nominally 0.1 a. 00 = oscillator is off. if cpsxrm = 1 (high range): 11 = oscillator is in high range: charge/discharge current is nominally 100 a. 10 = oscillator is in medium range. charge/discharge current is nominally 30 a. 01 = oscillator is in low range. charge/discharge current is nominally 9 a. 00 =oscillator is on; noise detection mode; no charge/discharge current is supplied. bit 1 cpsxout: capacitive sensing oscillator status bit 1 = oscillator is sourcing current (current flowing out of the pin) 0 = oscillator is sinking current (current flowing into the pin) bit 0 txxcs: timera/b external clock source select bit if tmrxcs = 1 : the txxcs bit controls which clock external to the core/timera/b module supplies timera/b: 1 = timera/b clock source is the capacitive sensing oscillator 0 = timera/b clock source is the txcki pin if tmrxcs = 0 : timera/b clock source is controlled by the core/timera/b module and is f osc /4.
? 2010 microchip technology inc. preliminary ds41418a-page 125 pic16f707/pic16lf707 register 16-2: cpsxcon1: capacitiv e sensing control register 1 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? cpsxch3 cpsxch2 cpsxch1 cpsxch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3-0 cpsxch<3:0>: capacitive sensing channel select bits if cpsxon = 0 : these bits are ignored. no channel is selected. if cpsxon = 1 : 0000 = channel 0, (cpsx0) 0001 = channel 1, (cpsx1) 0010 = channel 2, (cpsx2) 0011 = channel 3, (cpsx3) 0100 = channel 4, (cpsx4) 0101 = channel 5, (cpsx5) 0110 = channel 6, (cpsx6) 0111 = channel 7, (cpsx7) 1000 = channel 8, (cpsx8) 1001 = channel 9, (cpsx9) 1010 = channel 10, (cpsx10) 1011 = channel 11, (cpsx11) 1100 = channel 12, (cpsx12) 1101 = channel 13, (cpsx13) 1110 = channel 14, (cpsx14) 1111 = channel 15, (cpsx15)
pic16f707/pic16lf707 ds41418a-page 126 preliminary ? 2010 microchip technology inc. table 16-4: summary of registers as sociated with capacitive sensing name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansela ansa7 ansa6 ansa5 ansa4 ansa3 ansa2 ansa1 ansa0 1111 1111 1111 1111 anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 anseld ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 1111 1111 1111 1111 ansele ? ? ? ? ? anse2 anse1 anse0 ---- -111 ---- -111 cpsacon0 cpsaon cpsarm ? ? cpsarng1 cpsarng0 cpsaout taxcs 00-- 0000 00-- 0000 cpsacon1 ? ? ? ? cpsach3 cpsach2 cpsach1 cpsach0 ---- 0000 ---- 0000 cpsbcon0 cpsbon cpsbrm ? ? cpsbrng1 cpsbrng0 cpsbout tbxcs 00-- 0000 00-- 0000 cpsbcon1 ? ? ? ? cpsbch3 cpsbch2 cpsbch1 cpsbch0 ---- 0000 ---- 0000 tacon tmraon ? tacs tase tapsa taps2 taps1 taps0 0-00 0000 0-00 0000 tbcon tmrbon ? tbcs tbse tbpsa tbps2 tbps1 tbps0 0-00 0000 0-00 0000 t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ?tmr1on 0000 00-0 0000 00-0 t3con tmr3cs1 tmr3cs0 t3ckps1 t3ckps0 ? t3sync ?tmr3on 0000 -0-0 0000 -0-0 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 trisd trisd7 trisd6 trisd5 trisd 4 trisd3 trisd2 trisd1 trisd0 1111 1111 1111 1111 trise ? ? ? ? trise3 trise2 trise1 trise0 ---- 1111 ---- 1111 legend: ? = unimplemented locations, read as ?0?. shaded cells are not used by the capacitive sensing modules.
? 2010 microchip technology inc. preliminary ds41418a-page 127 pic16f707/pic16lf707 17.0 capture/compare/pwm (ccp) module the capture/compare/pwm module is a peripheral which allows the user to time and control different events. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate a pulse-width modulated signal of varying frequency and duty cycle. the timer resources used by the module are shown in table 17-2. additional information on ccp modules is available in application note an594, ?using the ccp modules? (ds00594). table 17-1: ccp mode ? timer resources required ccp mode timer resource capture timer1 compare timer1 pwm timer2 note: timer3 has no connection to either ccp. table 17-2: interaction of two ccp modules ccp1 mode ccp2 mode interaction capture capture same tmr1 time base capture compare same tmr1 time base (1, 2) compare compare same tmr1 time base (1, 2) pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). the rising edges will be aligned. pwm capture none pwm compare none note 1: if ccp2 is configured as a special event trigger, ccp1 will clear timer1, affecting the value captured on the ccp2 pin. 2: if ccp1 is in capture mode and ccp2 is configured as a special event trigger, ccp2 will clear timer1, affecting the value captured on the ccp1 pin. note: ccprx and ccpx throughout this document refer to ccpr1 or ccpr2 and ccp1 or ccp2, respectively.
pic16f707/pic16lf707 ds41418a-page 128 preliminary ? 2010 microchip technology inc. register 17-1: ccpxcon: ccpx control register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb<1:0> : pwm duty cycle least significant bits capture mode : unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm<3:0>: ccp mode select bits 0000 = capture/compare/pwm off (resets ccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (ccpxif bit of the pirx register is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit of the pirx register is set) 1001 = compare mode, clear output on match (ccpxif bit of the pirx register is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set of the pirx register, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit of the pirx register is set, tmr1 is reset and a/d conversion (1) is started if the adc module is enabled. ccpx pin is unaffected.) 11xx = pwm mode. note 1: a/d conversion start feature is available only on ccp2.
? 2010 microchip technology inc. preliminary ds41418a-page 129 pic16f707/pic16lf707 17.1 capture mode in capture mode, ccprxh:ccprxl captures the 16-bit value of the tmr1 register when an event occurs on pin ccpx. an event is defined as one of the following and is configured by the ccpxm<3:0> bits of the ccpxcon register: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge when a capture is made, the interrupt request flag bit ccpxif of the pirx register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccprxh, ccprxl register pair is read, the old captured value is overwritten by the new captured value (refer to figure 17-1). 17.1.1 ccpx pin configuration in capture mode, the ccpx pin should be configured as an input by setting the associated tris control bit. either rc1 or rb3 can be selected as the ccp2 pin. refer to section 6.1 ?alternate pin function? for more information. figure 17-1: capture mode operation block diagram 17.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode or when timer1 is clocked at f osc , the capture operation may not work. 17.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit of the piex register clear to avoid false interrupts. additionally, the user should clear the ccpxif interrupt flag bit of the pirx register following any change in operating mode. 17.1.4 ccp prescaler there are four prescaler settings specified by the ccpxm<3:0> bits of the ccpxcon register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccpxcon register before changing the prescaler (refer to example 17-1). example 17-1: changing between capture prescalers 17.1.5 capture during sleep capture mode depends upon the timer1 module for proper operation. there are two options for driving the timer1 module in capture mode. it can be driven by the instruction clock (f osc /4), or by an external clock source. if timer1 is clocked by f osc /4, then timer1 will not increment during sleep. when the device wakes from sleep, timer1 will continue from its previous state. if timer1 is clocked by an external clock source, then capture mode will operate as defined in section 17.1 ?capture mode? . note: if the ccpx pin is configured as an output, a write to the port can cause a capture condition. ccprxh ccprxl tmr1h tmr1l set flag bit ccpxif (pirx register) capture enable ccpxcon<3:0> prescaler ? 1, 4, 16 and edge detect ccpx system clock (f osc ) note: clocking timer1 from the system clock (f osc ) should not be used in capture mode. in order for capture mode to recognize the trigger event on the ccpx pin, timer1 must be clocked from the instruction clock (f osc /4) or from an external clock source. banksel ccp1con ;set bank bits to point ;to ccp1con clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value
pic16f707/pic16lf707 ds41418a-page 130 preliminary ? 2010 microchip technology inc. table 17-3: summary of registers associated with capture name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 ccprxl capture/compare/pwm register x low byte xxxx xxxx uuuu uuuu ccprxh capture/compare/pwm register x high byte xxxx xxxx uuuu uuuu intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pie2 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie 0000 ---0 0000 ---0 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pir2 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if 0000 ---0 0000 ---0 t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss1 t1gss0 0000 0x00 0000 0x00 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: - = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the capture.
? 2010 microchip technology inc. preliminary ds41418a-page 131 pic16f707/pic16lf707 17.2 compare mode in compare mode, the 16-bit ccprx register value is constantly compared against the tmr1 register pair value. when a match occurs, the ccpx module may: ? toggle the ccpx output ? set the ccpx output ? clear the ccpx output ? generate a special event trigger ? generate a software interrupt the action on the pin is based on the value of the ccpxm<3:0> control bits of the ccpxcon register. all compare modes can generate an interrupt. figure 17-2: compare mode operation block diagram 17.2.1 ccpx pin configuration the user must configure the ccpx pin as an output by clearing the associated tris bit. either rc1 or rb3 can be selected as the ccp2 pin. refer to section 6.1 ?alternate pin function? for more information. 17.2.2 timer1 mode selection in compare mode, timer1 must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. 17.2.3 software interrupt mode when software interrupt mode is chosen (ccpxm<3:0> = 1010 ), the ccpxif bit in the pirx register is set and the ccpx module does not assert control of the ccpx pin (refer to the ccpxcon register). 17.2.4 special event trigger when special event trigger mode is chosen (ccpxm<3:0> = 1011 ), the ccpx module does the following: ? resets timer1 ? starts an adc conversion if adc is enabled (ccp2 only) the ccpx module does not assert control of the ccpx pin in this mode (refer to the ccpxcon register). the special event trigger output of the ccp occurs immediately upon a match between the tmr1h, tmr1l register pair and the ccprxh, ccprxl register pair. the tmr1h, tmr1l register pair is not reset until the next rising edge of the timer1 clock. this allows the ccprxh, ccprxl register pair to effectively provide a 16-bit programmable period register for timer1. 17.2.5 compare during sleep the compare mode is dependent upon the system clock (f osc ) for proper operation. since f osc is shut down during sleep mode, the compare mode will not function properly during sleep. note: clearing the ccpxcon register will force the ccpx compare output latch to the default low level. this is not the port i/o data latch. ccprxh ccprxl tmr1h tmr1l comparator qs r output logic special event trigger set ccpxif interrupt flag (pirx) match tris ccpxcon<3:0> mode select output enable special event trigger will: ? clear tmr1h and tmr1l registers. ? not set interrupt flag bit tmr1if of the pir1 register. ? set the go/done bit to start the adc conversion (ccp2 only). ccpx 4 note: clocking timer1 from the system clock (f osc ) should not be used in compare mode. for the compare operation of the tmr1 register to the ccprx register to occur, timer1 must be clocked from the instruction clock (f osc /4) or from an external clock source. note 1: the special event trigger from the ccp module does not set interrupt flag bit tmr1if of the pir1 register. 2: removing the match condition by changing the contents of the ccprxh and ccprxl register pair, between the clock edge that generates the special event trigger and the clock edge that generates the timer1 reset, will preclude the reset from occurring.
pic16f707/pic16lf707 ds41418a-page 132 preliminary ? 2010 microchip technology inc. table 17-4: summary of regist ers associated with compare name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 ccprxl capture/compare/pwm register x low byte xxxx xxxx uuuu uuuu ccprxh capture/compare/pwm register x high byte xxxx xxxx uuuu uuuu intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pie2 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie 0000 ---0 0000 ---0 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pir2 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if 0000 ---0 0000 ---0 t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss1 t1gss0 0000 0x00 0000 0x00 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: - = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the compare.
? 2010 microchip technology inc. preliminary ds41418a-page 133 pic16f707/pic16lf707 17.3 pwm mode the pwm mode generates a pulse-width modulated signal on the ccpx pin. the duty cycle, period and resolution are determined by the following registers: ?pr2 ?t2con ? ccprxl ? ccpxcon in pulse-width modulation (pwm) mode, the ccp module produces up to a 10-bit resolution pwm output on the ccpx pin. figure 17-3 shows a simplified block diagram of pwm operation. figure 17-4 shows a typical waveform of the pwm signal. for a step-by-step procedure on how to set up the ccp module for pwm operation, refer to section 17.3.8 ?setup for pwm operation? . figure 17-3: simplified pwm block diagram the pwm output (figure 17-4) has a time base (period) and a time that the output stays high (duty cycle). figure 17-4: ccp pwm output 17.3.1 ccpx pin configuration in pwm mode, the ccpx pin is multiplexed with the port data latch. the user must configure the ccpx pin as an output by clearing the associated tris bit. either rc1 or rb3 can be selected as the ccp2 pin. refer to section 6.1 ?alternate pin function? for more information. ccprxl ccpr x h (2) (slave) comparator tmr2 pr2 (1) rq s duty cycle registers ccpxcon<5:4> clear timer2, toggle ccp x pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. 2: in pwm mode, ccprxh is a read-only register. tris ccpx comparator note: clearing the ccpxcon register will relinquish ccpx control of the ccpx pin. period pulse width tmr2 = 0 tmr2 = ccprxl:ccpxcon<5:4> tmr2 = pr2
pic16f707/pic16lf707 ds41418a-page 134 preliminary ? 2010 microchip technology inc. 17.3.2 pwm period the pwm period is specified by the pr2 register of timer2. the pwm period can be calculated using the formula of equation 17-1. equation 17-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ? tmr2 is cleared ? the ccpx pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) ? the pwm duty cycle is latched from ccprxl into ccprxh. 17.3.3 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to multiple registers: ccprxl register and dcxb<1:0> bits of the ccpxcon register. the ccprxl contains the eight msbs and the dcxb<1:0> bits of the ccpxcon register contain the two lsbs. ccprxl and dcxb<1:0> bits of the ccpxcon register can be written to at any time. the duty cycle value is not latched into ccprxh until after the period completes (i.e., a match between pr2 and tmr2 registers occurs). while using the pwm, the ccprxh register is read-only. equation 17-2 is used to calculate the pwm pulse width. equation 17-3 is used to calculate the pwm duty cycle ratio. equation 17-2: pulse width equation 17-3: duty cycle ratio the ccprxh register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmr2 register is concatenated with either the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. when the 10-bit time base matches the ccprxh and 2-bit latch, then the ccpx pin is cleared (refer to figure 17-3). note: the timer2 postscaler (refer to section 15.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. pwm period pr2 ?? 1 + ?? 4t osc ? ? ? = (tmr2 prescale value) note: t osc = 1/f osc pulse width ccprxl:ccpxcon<5:4> ?? ? = t osc ? (tmr2 prescale value) note: t osc = 1/f osc duty cycle ratio ccprxl:ccpxcon<5:4> ?? 4pr2 1 + ?? ---------------------------------------------------------------------- - =
? 2010 microchip technology inc. preliminary ds41418a-page 135 pic16f707/pic16lf707 17.3.4 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is 10 bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 17-4. equation 17-4: pwm resolution 17.3.5 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the ccpx pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 17.3.6 changes in system clock frequency the pwm frequency is derived from the system clock frequency (f osc ). any changes in the system clock fre- quency will result in changes to the pwm frequency. refer to section 7.0 ?oscillator module? for additional details. 17.3.7 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. 17.3.8 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. disable the pwm pin (ccpx) output driver(s) by setting the associated tris bit(s). 2. load the pr2 register with the pwm period value. 3. configure the ccp module for the pwm mode by loading the ccpxcon register with the appropriate values. 4. load the ccprxl register and the dcxbx bits of the ccpxcon register, with the pwm duty cycle value. 5. configure and start timer2: ? clear the tmr2if interrupt flag bit of the pir1 register. see note below. ? configure the t2ckps bits of the t2con register with the timer2 prescale value. ? enable timer2 by setting the tmr2on bit of the t2con register. 6. enable pwm output pin: ? wait until timer2 overflows, tmr2if bit of the pir1 register is set. see note below. ? enable the pwm pin (ccpx) output driver(s) by clearing the associated tris bit(s). note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4pr2 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = table 17-5: example pwm frequencies and resolutions (f osc = 20 mhz) pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 table 17-6: example pwm frequencies and resolutions (f osc = 8 mhz) pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5 note: in order to send a complete duty cycle and period on the first pwm output, the above steps must be included in the setup sequence. if it is not critical to start with a complete pwm signal on the first output, then step 6 may be ignored.
pic16f707/pic16lf707 ds41418a-page 136 preliminary ? 2010 microchip technology inc. table 17-7: summary of registers associated with pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets anselb ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 1111 1111 1111 1111 anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 ccprxl capture/compare/pwm register x low byte xxxx xxxx uuuu uuuu ccprxh capture/compare/pwm register x high byte xxxx xxxx uuuu uuuu pr2 timer2 period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 tmr2 timer2 module register 0000 0000 0000 0000 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: - = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the pwm.
? 2010 microchip technology inc. preliminary ds41418a-page 137 pic16f707/pic16lf707 18.0 addressable universal synchronous asynchronous receiver transmitter (ausart) the addressable universal synchronous asynchronous receiver transmitter (ausart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the ausart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the ausart module includes the following capabilities: ? full-duplex asynchronous transmit and receive ? two-character input buffer ? one-character output buffer ? programmable 8-bit or 9-bit character length ? address detection in 9-bit mode ? input buffer overrun error detection ? received character framing error detection ? half-duplex synchronous master ? half-duplex synchronous slave ? sleep operation block diagrams of the ausart transmitter and receiver are shown in figure 18-1 and figure 18-2. figure 18-1: ausart transmit block diagram txif txie interrupt txen tx9d msb lsb data bus txreg register transmit shift register (tsr) (8) 0 tx9 trmt spen tx/ck pin buffer and control 8 spbrg f osc n n + 1 multiplier x4 x16 x64 sync 100 brgh x10 baud rate generator ???
pic16f707/pic16lf707 ds41418a-page 138 preliminary ? 2010 microchip technology inc. figure 18-2: ausart recei ve block diagram the operation of the ausart module is controlled through two registers: ? transmit status and control (txsta) ? receive status and control (rcsta) these registers are detailed in register 18-1 and register 18-2, respectively. rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? spbrg f osc n n + 1 multiplier x4 x16 x64 sync 100 brgh x10 baud rate generator
? 2010 microchip technology inc. preliminary ds41418a-page 139 pic16f707/pic16lf707 18.1 ausart asynchronous mode the ausart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a ? 1 ? data bit, and a v ol space state which represents a ? 0 ? data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is 8 bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. refer to table 18-5 for examples of baud rate configurations. the ausart transmits and receives the lsb first. the ausart?s transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 18.1.1 ausart asynchronous transmitter the ausart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txreg register. 18.1.1.1 enabling the transmitter the ausart transmitter is enabled for asynchronous operations by configuring the following three control bits: ?txen = 1 ? sync = 0 ? spen = 1 all other ausart control bits are assumed to be in their default state. setting the txen bit of the txsta register enables the transmitter circuitry of the ausart. clearing the sync bit of the txsta register configures the ausart for asynchronous operation. setting the spen bit of the rcsta register enables the ausart and automatically configures the tx/ck i/o pin as an output. 18.1.1.2 transmitting data a transmission is initiated by writing a character to the txreg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txreg until the stop bit of the previous character has been transmitted. the pending character in the txreg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txreg. 18.1.1.3 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the ausart transmitter is enabled and no character is being held for transmission in the txreg. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txreg. the txif flag bit is not cleared immediately upon writing txreg. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the txreg write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the txreg is empty, regardless of the state of txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the txreg. note 1: when the spen bit is set, the rx/dt i/o pin is automatically configured as an input, regardless of the state of the corresponding tris bit and whether or not the ausart receiver is enabled. the rx/dt pin data can be read via a normal port read but port latch data output is precluded. 2: the corresponding ansel bit must be cleared for the rx/dt port pin to ensure proper ausart functionality. 3: the txif transmitter interrupt flag is set when the txen enable bit is set.
pic16f707/pic16lf707 ds41418a-page 140 preliminary ? 2010 microchip technology inc. 18.1.1.4 tsr status the trmt bit of the txsta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txreg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user has to poll this bit to determine the tsr status. 18.1.1.5 transmitting 9-bit characters the ausart supports 9-bit character transmissions. when the tx9 bit of the txsta register is set the ausart will shift 9 bits out for each character transmit- ted. the tx9d bit of the txsta register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the 8 least significant bits into the txreg. all nine bits of data will be transferred to the tsr shift register immediately after the txreg is written. a special 9-bit address mode is available for use with multiple receivers. refer to section 18.1.2.7 ?address detection? for more information on the address mode. 18.1.1.6 asynchronous transmission set-up: 1. initialize the spbrg register and the brgh bit to achieve the desired baud rate (refer to section 18.2 ?ausart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if 9-bit transmission is desired, set the tx9 con- trol bit. a set ninth data bit will indicate that the 8 least significant data bits are an address when the receiver is set for address detection. 4. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 5. if interrupts are desired, set the txie interrupt enable bit of the pie1 register. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 6. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 7. load 8-bit data into the txreg register. this will start the transmission. figure 18-3: asynchronous transmission figure 18-4: asynchronous transmiss ion (back-to-back) note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx/ck pin txif bit (transmit buffer empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy transmit shift reg. write to txreg brg output (shift clock) tx/ck pin trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy txif bit (transmit buffer empty flag)
? 2010 microchip technology inc. preliminary ds41418a-page 141 pic16f707/pic16lf707 18.1.2 ausart asynchronous receiver the asynchronous mode is typically used in rs-232 systems. the receiver block diagram is shown in figure 18-2. the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character first-in first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the ausart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcreg register. 18.1.2.1 enabling the receiver the ausart receiver is enabled for asynchronous operation by configuring the following three control bits: ? cren = 1 ? sync = 0 ? spen = 1 all other ausart control bits are assumed to be in their default state. setting the cren bit of the rcsta register enables the receiver circuitry of the ausart. clearing the sync bit of the txsta register configures the ausart for asynchronous operation. setting the spen bit of the rcsta register enables the ausart and automatically configures the rx/dt i/o pin as an input. table 18-1: registers associated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x spbrg brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 0000 0000 0000 0000 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 txreg ausart transmit data register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: when the spen bit is set, the tx/ck i/o pin is automatically configured as an out- put, regardless of the state of the corre- sponding tris bit and whether or not the ausart transmitter is enabled. the port latch is disconnected from the out- put driver so it is not possible to use the tx/ck pin as a general purpose output. 2: the corresponding ansel bit must be cleared for the rx/dt port pin to ensure proper ausart functionality.
pic16f707/pic16lf707 ds41418a-page 142 preliminary ? 2010 microchip technology inc. 18.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting ? 0 ? or ? 1 ? is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a ? 1 ?. if the data recovery circuit samples a ? 0 ? in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. refer to section 18.1.2.4 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the ausart receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rcreg register. 18.1.2.3 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the ausart receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting all of the following bits: ? rcie, receive interrupt enable bit of the pie1 register ? peie, peripheral interrupt enable bit of the intcon register ? gie, global interrupt enable bit of the intcon register the rcif interrupt flag bit of the pir1 register will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. 18.1.2.4 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcsta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcreg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcsta register which resets the ausart. clearing the cren bit of the rcsta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 18.1.2.5 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcsta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcsta register or by setting the ausart by clearing the spen bit of the rcsta register. 18.1.2.6 receiving 9-bit characters the ausart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the ausart will shift 9 bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcreg. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. refer to section 18.1.2.5 ?receive overrun error? for more information on overrun errors. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcreg will not clear the ferr bit.
? 2010 microchip technology inc. preliminary ds41418a-page 143 pic16f707/pic16lf707 18.1.2.7 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcsta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit of the pir1 register. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. 18.1.2.8 asynchronous reception set-up: 1. initialize the spbrg register and the brgh bit to achieve the desired baud rate (refer to section 18.2 ?ausart baud rate generator (brg)? ). 2. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 3. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 4. if 9-bit reception is desired, set the rx9 bit. 5. enable reception by setting the cren bit. 6. the rcif interrupt flag bit of the pir1 register will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie bit of the pie1 register was also set. 7. read the rcsta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 8. get the received 8 least significant data bits from the receive buffer by reading the rcreg register. 9. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 18.1.2.9 9-bit address detection mode set- up this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrg register and the brgh bit to achieve the desired baud rate (refer to section 18.2 ?ausart baud rate generator (brg)? ). 2. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 3. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 4. enable 9-bit reception by setting the rx9 bit. 5. enable address detection by setting the adden bit. 6. enable reception by setting the cren bit. 7. the rcif interrupt flag bit of the pir1 register will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie inter- rupt enable bit of the pie1 register was also set. 8. read the rcsta register to get the error flags. the ninth data bit will always be set. 9. get the received 8 least significant data bits from the receive buffer by reading the rcreg register. software determines if this is the device?s address. 10. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts.
pic16f707/pic16lf707 ds41418a-page 144 preliminary ? 2010 microchip technology inc. figure 18-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. table 18-2: registers associated with asynchronous reception name bit 7 bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on por, bor value on all other resets anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 rcreg ausart receive data register 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x spbrg brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 0000 0000 0000 0000 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used for asynchronous reception.
? 2010 microchip technology inc. preliminary ds41418a-page 145 pic16f707/pic16lf707 register 18-1: txsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync ? brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode : don?t care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: ausart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in synchronous mode.
pic16f707/pic16lf707 ds41418a-page 146 preliminary ? 2010 microchip technology inc. register 18-2: rcsta: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit (1) 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care synchronous mode ? master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : don?t care synchronous mode : must be set to ? 0 ? bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. note 1: the ausart module automatically changes the pin from tri-state to drive as needed. configure trisx = 1 .
? 2010 microchip technology inc. preliminary ds41418a-page 147 pic16f707/pic16lf707 18.2 ausart baud rate generator (brg) the baud rate generator (brg) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous ausart operation. the spbrg register determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by the brgh bit of the txsta register. in synchronous mode, the brgh bit is ignored. table 18-3 contains the formulas for determining the baud rate. example 18-1 provides a sample calculation for determining the baud rate and baud rate error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 18-5. it may be advantageous to use the high baud rate (brgh = 1 ), to reduce the baud rate error. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. example 18-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, and asynchronous mode with sync = 0 and brgh = 0 (as seen in table 18-5): solving for spbrg: spbrg f osc 64 desired baud rate ?? --------------------------------------------------------- ?? ?? 1 ? = desired baud rate f osc 64 spbrg 1 + ?? --------------------------------------- = 16000000 64 9600 ?? ------------------------ ?? ?? 1 ? = 25.042 ?? 25 == actual baud rate 16000000 64 25 1 + ?? -------------------------- - = 9615 = error actual baud rate desired baud rate ? desired baud rate ------------------------------------------------------------------------------------------------- - ?? ?? 100 = 9615 9600 ? 9600 ----------------------------- - ?? ?? 100 0.16% == % table 18-3: baud rate formulas configuration bits ausart mode baud rate formula sync brgh 00 asynchronous f osc /[64 (n+1)] 01 asynchronous f osc /[16 (n+1)] 1x synchronous f osc /[4 (n+1)] legend: x = don?t care, n = value of spbrg register table 18-4: registers associated with the baud rate generator namebit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on por, bor value on all other resets rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x spbrg brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 0000 0000 0000 0000 txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used for the baud rate generator.
pic16f707/pic16lf707 ds41418a-page 148 preliminary ? 2010 microchip technology inc. table 18-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.0000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ? ? ? ? ? ? ?? ? ?? ? 1200 1221 1.73 255 1200 0.00 239 1201 0.08 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2403 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10416 -0.01 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k ? ? ? 57.60k 0.00 7 ?? ? 57.60k 0.00 2 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ? ? ? 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 ? ? ? 9600 9615 0.16 12 ? ? ? 9600 0.00 5 ? ? ? 10417 10417 0.00 11 10417 0.00 5 ? ? ? ? ? ? 19.2k ? ? ? ? ? ? 19.20k 0.00 2 ? ? ? 57.6k ? ? ? ? ? ? 57.60k 0.00 0 ? ? ? 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.0000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ?? ? ?? ? ?? ? 1200 ? ? ? ? ? ? ? ? ? ? ? ? 2400 ? ? ? ? ? ? ? ? ? ?? ? 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.8k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 ? ? ? 115.2k 0.00 5
? 2010 microchip technology inc. preliminary ds41418a-page 149 pic16f707/pic16lf707 baud rate sync = 0 , brgh = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ? ? ? ? ? ? 300 0.16 207 1200 ? ? ? 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? table 18-5: baud rates for asynchronous modes
pic16f707/pic16lf707 ds41418a-page 150 preliminary ? 2010 microchip technology inc. 18.3 ausart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary cir- cuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. there are two signal lines in synchronous mode: a bidirectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and trans- mit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the ausart can operate as either a master or slave device. start and stop bits are not used in synchronous transmissions. 18.3.1 synchronous master mode the following bits are used to configure the ausart for synchronous master operation: ? sync = 1 ? csrc = 1 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. setting the csrc bit of the txsta register configures the device as a master. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the ausart. 18.3.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device config- ured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the ausart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trail- ing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are generated as there are data bits. 18.3.1.2 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automatically enabled when the ausart is configured for synchronous master transmit operation. a transmission is initiated by writing a character to the txreg register. if the tsr still contains all or part of a previous character, the new character data is held in the txreg until the last bit of the previous character has been transmitted. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately trans- ferred to the tsr. the transmission of the character commences immediately following the transfer of the data to the tsr from the txreg. each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. 18.3.1.3 synchronous master transmission set-up: 1. initialize the spbrg register and the brgh bit to achieve the desired baud rate (refer to section 18.2 ?ausart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. disable receive mode by clearing bits sren and cren. 4. enable transmit mode by setting the txen bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 8. start transmission by loading data to the txreg register. note: the tsr register is not mapped in data memory, so it is not available to the user.
? 2010 microchip technology inc. preliminary ds41418a-page 151 pic16f707/pic16lf707 figure 18-6: synchronous t ransmission figure 18-7: synchronous transmission (through txen) bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: synchronous master mode, spbrg = 0 , continuous transmission of two 8-bit words. pin tx/ck pin rx/dt pin tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit table 18-6: registers associated wi th synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x spbrg brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 0000 0000 0000 0000 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 txreg ausart transmit data register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used for synchronous master transmission.
pic16f707/pic16lf707 ds41418a-page 152 preliminary ? 2010 microchip technology inc. 18.3.1.4 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver is automatically disabled when the ausart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcsta register) or the continuous receive enable bit (cren of the rcsta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit of the pir1 register is set and the character is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcreg. the rcif bit remains set as long as there are un-read characters in the receive fifo. 18.3.1.5 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ck pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 18.3.1.6 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcreg is read to access the fifo. when this happens the oerr bit of the rcsta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcreg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcsta register. 18.3.1.7 receiving 9-bit characters the ausart supports 9-bit character reception. when the rx9 bit of the rcsta register is set, the ausart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcreg. address detection in synchronous modes is not supported, therefore the adden bit of the rcsta register must be cleared. 18.3.1.8 synchronous master reception set-up: 1. initialize the spbrg register for the appropriate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set bit rx9. 6. verify address detection is disabled by clearing the adden bit of the rcsta register. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif of the pir1 register will be set when reception of a character is complete. an interrupt will be generated if the rcie inter- rupt enable bit of the pie1 register was set. 9. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcreg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit, which resets the ausart.
? 2010 microchip technology inc. preliminary ds41418a-page 153 pic16f707/pic16lf707 figure 18-8: synchronous reception (master mode, sren) cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rcreg ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? note: timing diagram demonstrates synchronous master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin pin table 18-7: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 rcreg ausart receive data register 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used for synchronous master reception.
pic16f707/pic16lf707 ds41418a-page 154 preliminary ? 2010 microchip technology inc. 18.3.2 synchronous slave mode the following bits are used to configure the ausart for synchronous slave operation: ? sync = 1 ? csrc = 0 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. clearing the csrc bit of the txsta register configures the device as a slave. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the ausart. 18.3.2.1 ausart synchronous slave transmit the operation of the synchronous master and slave modes are identical (refer to section 18.3.1.2 ?synchronous master transmission?) , except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in txreg register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the txreg register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 18.3.2.2 synchronous slave transmission set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the cren and sren bits. 3. if using interrupts, ensure that the gie and peie bits of the intcon register are set and set the txie bit. 4. if 9-bit transmission is desired, set the tx9 bit. 5. enable transmission by setting the txen bit. 6. verify address detection is disabled by clearing the adden bit of the rcsta register. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant 8 bits to the txreg register. table 18-8: registers associated with synchronous slave transmission name bit 7 bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on por, bor value on all other resets anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 txreg ausart transmit data register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used fo r synchronous slave transmission.
? 2010 microchip technology inc. preliminary ds41418a-page 155 pic16f707/pic16lf707 18.3.2.3 ausart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 18.3.1.4 ?synchronous master reception? ), with the following exceptions: ? sleep ? cren bit is always set, therefore the receiver is never idle ? sren bit, which is a ?don?t care? in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcreg register. if the rcie interrupt enable bit of the pie1 register is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 18.3.2.4 synchronous slave reception set- up: 1. set the sync and spen bits and clear the csrc bit. 2. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 3. if 9-bit reception is desired, set the rx9 bit. 4. verify address detection is disabled by clearing the adden bit of the rcsta register. 5. set the cren bit to enable reception. 6. the rcif bit of the pir1 register will be set when reception is complete. an interrupt will be generated if the rcie bit of the pie1 register was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcsta register. 8. retrieve the 8 least significant bits from the receive fifo by reading the rcreg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register. table 18-9: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets anselc ansc7 ansc6 ansc5 ? ? ansc2 ansc1 ansc0 111- -111 111- -111 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 rcreg ausart receive data register 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 legend: x = unknown, - = unimplemented read as ? 0 ?. shaded cells are not used fo r synchronous slave reception.
pic16f707/pic16lf707 ds41418a-page 156 preliminary ? 2010 microchip technology inc. 18.4 ausart operation during sleep the ausart will remain active during sleep only in the synchronous slave mode. all other modes require the system clock and therefore cannot generate the necessary signals to run the transmit or receive shift registers during sleep. synchronous slave mode uses an externally generated clock to run the transmit and receive shift registers. 18.4.1 synchronous receive during sleep to receive during sleep, all the following conditions must be met before entering sleep mode: ? rcsta and txsta control registers must be configured for synchronous slave reception (refer to section 18.3.2.4 ?synchronous slave reception set-up:? ). ? if interrupts are desired, set the rcie bit of the pie1 register and the peie bit of the intcon register. ? the rcif interrupt flag must be cleared by read- ing rcreg to unload any pending characters in the receive buffer. upon entering sleep mode, the device will be ready to accept data and clocks on the rx/dt and tx/ck pins, respectively. when the data word has been completely clocked in by the external device, the rcif interrupt flag bit of the pir1 register will be set. thereby, waking the processor from sleep. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit of the intcon register is also set, then the interrupt service routine at address 0004h will be called. 18.4.2 synchronous transmit during sleep to transmit during sleep, all the following conditions must be met before entering sleep mode: ? rcsta and txsta control registers must be configured for synchronous slave transmission (refer to section 18.3.2.2 ?synchronous slave transmission set-up:? ). ? the txif interrupt flag must be cleared by writing the output data to the txreg, thereby filling the tsr and transmit buffer. ? if interrupts are desired, set the txie bit of the pie1 register and the peie bit of the intcon register. upon entering sleep mode, the device will be ready to accept clocks on tx/ck pin and transmit data on the rx/dt pin. when the data word in the tsr has been completely clocked out by the external device, the pending byte in the txreg will transfer to the tsr and the txif flag will be set. thereby, waking the processor from sleep. at this point, the txreg is available to accept another character for transmission, which will clear the txif flag. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit is also set then the interrupt service routine at address 0004h will be called.
? 2010 microchip technology inc. preliminary ds41418a-page 157 pic16f707/pic16lf707 19.0 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other peripher- als or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) 19.1 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. the ssp module can be operated in one of two spi modes: ?master mode ? slave mode spi is a full-duplex protocol, with all communication being bidirectional and initiated by a master device. all clocking is provided by the master device and all bits are transmitted, msb first. care must be taken to ensure that all devices on the spi bus are setup to allow all controllers to send and receive data at the same time. a typical spi connection between microcontroller devices is shown in figure 19-1. addressing of more than one slave device is accomplished via multiple hardware slave select lines. external hardware and additional i/o pins must be used to support multiple slave select addressing. this prevents extra overhead in software for communication. for spi communication, typically three pins are used: ? serial data out (sdo) ? serial data in (sdi) ? serial clock (sck) additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) figure 19-1: typical spi mast er/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm<3:0> = 00xx serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm<3:0> = 010x serial clock ss slave select general i/o (optional)
pic16f707/pic16lf707 ds41418a-page 158 preliminary ? 2010 microchip technology inc. figure 19-2: spi mode block diagram 19.1.1 master mode in master mode, data transfer can be initiated at any time because the master controls the sck line. master mode determines when the slave (figure 19-1, processor 2) transmits data via control of the sck line. 19.1.1.1 master mode operation the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr register shifts the data in and out of the device, msb first. the sspbuf register holds the data that is written out of the master until the received data is ready. once the eight bits of data have been received, the byte is moved to the sspbuf register. the buffer full status bit, bf of the sspstat register, and the ssp interrupt flag bit, sspif of the pir1 register, are then set. any write to the sspbuf register during transmission/ reception of data will be ignored and the write collision detect bit, wcol of the sspcon register, will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data is written to the sspbuf. the bf bit of the sspstat register is set when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. the ssp interrupt may be used to determine when the transmission/reception is complete and the sspbuf must be read and/or written. if interrupts are not used, then software polling can be done to ensure that a write collision does not occur. example 19-1 shows the loading of the sspbuf (sspsr) for data transmission. 19.1.1.2 enabling master i/o to enable the serial port, the sspen bit of the sspcon register, must be set. to reset or reconfigure spi mode, clear the sspen bit, re-initialize the sspcon register and then set the sspen bit. if a master mode of operation is selected in the sspm bits of the sspcon register, the sdi, sdo and sck pins will be assigned as serial port pins. for these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated tris register as follows: ? sdi configured as input ? sdo configured as output ? sck configured as output read write internal data bus sdi sdo ra5/ss sck sspsr reg sspbuf reg sspm<3:0> bit 0 shift clock ss control enable edge select clock select tmr2 f osc prescaler 4, 16, 64 trisx 2 4 ra0/ss sssel output ? 2 edge select bit 7 note: the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register.
? 2010 microchip technology inc. preliminary ds41418a-page 159 pic16f707/pic16lf707 19.1.1.3 master mode setup in master mode, the data is transmitted/received as soon as the sspbuf register is loaded with a byte value. if the master is only going to receive, sdo output could be disabled (programmed and used as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. when initializing spi master mode operation, several options need to be specified. this is accomplished by programming the appropriate control bits in the sspcon and sspstat registers. these control bits allow the following to be specified: ? sck as clock output ? idle state of sck (ckp bit) ? data input sample phase (smp bit) ? output data on rising/falling edge of sck (cke bit) ? clock bit rate in master mode, the spi clock rate (bit rate) is user selectable to be one of the following: ?f osc /4 (or tcy) ?f osc /16 (or 4 ? tcy) ?f osc /64 (or 16 ? tcy) ? (timer2 output)/2 this allows a maximum data rate of 5 mbps (at f osc =20mhz). figure 19-3 shows the waveforms for master mode. the clock polarity is selected by appropriately program- ming the ckp bit of the sspcon register. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the sample time of the input data is shown based on the state of the smp bit and can occur at the middle or end of the data output time. the time when the sspbuf is loaded with the received data is shown. 19.1.1.4 sleep in master mode in master mode, all module clocks are halted and the transmission/reception will remain in their current state, paused, until the device wakes from sleep. after the device wakes up from sleep, the module will continue to transmit/receive data.
pic16f707/pic16lf707 ds41418a-page 160 preliminary ? 2010 microchip technology inc. figure 19-3: spi master mode waveform example 19-1: loading the sspbuf (sspsr) register sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) banksel sspstat ; loop btfss sspstat, bf ;has data been received(transmit complete)? goto loop ;no banksel sspbuf ; movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 2010 microchip technology inc. preliminary ds41418a-page 161 pic16f707/pic16lf707 19.1.2 slave mode for any spi device acting as a slave, the data is transmitted and received as external clock pulses appear on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. 19.1.2.1 slave mode operation the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. the slave has no control as to when data will be clocked in or out of the device. all data that is to be transmitted, to a master or another slave, must be loaded into the sspbuf register before the first clock pulse is received. once eight bits of data have been received: ? received byte is moved to the sspbuf register ? bf bit of the sspstat register is set ? sspif bit of the pir1 register is set any write to the sspbuf register during transmission/ reception of data will be ignored and the write collision detect bit, wcol of the sspcon register, will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed successfully. the user?s firmware must read sspbuf, clearing the bf flag, or the sspov bit of the sspcon register will be set with the reception of the next byte and communication will be disabled. a spi module transmits and receives at the same time, occasionally causing dummy data to be transmitted/ received. it is up to the user to determine which data is to be used and what can be discarded. 19.1.2.2 enabling slave i/o to enable the serial port, the sspen bit of the sspcon register must be set. if a slave mode of operation is selected in the sspm bits of the sspcon register, the sdi, sdo and sck pins will be assigned as serial port pins. for these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated tris register as follows: ? sdi configured as input ? sdo configured as output ? sck configured as input optionally, a fourth pin, slave select (ss ) may be used in slave mode. slave select may be configured to operate on one of the following pins via the sssel bit in the apfcon register. ?ra5/an4/ss ?ra0/an0/ss upon selection of a slave select pin, the appropriate bits must be set in the ansela and trisa registers. slave select must be set as an input by setting the corresponding bit in trisa, and digital i/o must be enabled on the ss pin by clearing the corresponding bit of the ansela register. 19.1.2.3 slave mode setup when initializing the ssp module to spi slave mode, compatibility must be ensured with the master device. this is done by programming the appropriate control bits of the sspcon and sspstat registers. these control bits allow the following to be specified: ? sck as clock input ? idle state of sck (ckp bit) ? data input sample phase (smp bit) ? output data on rising/falling edge of sck (cke bit) figure 19-4 and figure 19-5 show example waveforms of slave mode operation.
pic16f707/pic16lf707 ds41418a-page 162 preliminary ? 2010 microchip technology inc. figure 19-4: spi mode waveform (slave mode with cke = 0 ) figure 19-5: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional
? 2010 microchip technology inc. preliminary ds41418a-page 163 pic16f707/pic16lf707 19.1.2.4 slave select operation the ss pin allows synchronous slave mode operation. the spi must be in slave mode with ss pin control enabled (sspm<3:0> = 0100 ). the associated tris bit for the ss pin must be set, making ss an input. in slave select mode, when: ?ss = 0 , the device operates as specified in section 19.1.2 ?slave mode? . ?ss = 1 , the spi module is held in reset and the sdo pin will be tri-stated. when the spi module resets, the bit counter is cleared to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. figure 19-6 shows the timing waveform for such a synchronization event. 19.1.2.5 sleep in slave mode while in sleep mode, the slave can transmit/receive data. the spi transmit/receive shift register operates asynchronously to the device on the externally supplied clock source. this allows the device to be placed in sleep mode and data to be shifted into the spi trans- mit/receive shift register. when all 8 bits have been received, the ssp interrupt flag bit will be set and if enabled, will wake the device from sleep. figure 19-6: slave select synchro nization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspm<3:0> = 0100 ), the spi module will reset if the ss pin is driven high. 2: if the spi is used in slave mode with cke set, the ss pin control must be enabled. note: sspsr must be reinitialized by writing to the sspbuf register before the data can be clocked out of the slave again. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 sspsr must be reinitialized by writing to the sspbuf register before the data can be clocked out of the slave again.
pic16f707/pic16lf707 ds41418a-page 164 preliminary ? 2010 microchip technology inc. register 19-1: sspcon: sync serial po rt control register (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive overflow indicator bit 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the over- flow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no overflow bit 5 sspen : synchronous serial port enable bit 1 = enables serial port and configures sck, sdo and sdi as serial port pins (1) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp : clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm<3:0> : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. note 1: when enabled, these pins must be properly configured as input or output.
? 2010 microchip technology inc. preliminary ds41418a-page 165 pic16f707/pic16lf707 register 19-2: sspstat: sync serial port status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp : spi data input sample phase bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode bit 6 cke : spi clock edge select bit spi mode, ckp = 0 : 1 = data stable on rising edge of sck 0 = data stable on falling edge of sck spi mode, ckp = 1 : 1 = data stable on falling edge of sck 0 = data stable on rising edge of sck bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write information bit used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf : buffer full status bit 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty
pic16f707/pic16lf707 ds41418a-page 166 preliminary ? 2010 microchip technology inc. table 19-1: summary of registers associated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansela ansa7 ansa6 ansa5 ansa4 ansa3 ansa2 ansa1 ansa0 1111 1111 1111 1111 apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000x pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pr2 timer2 period register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the ssp in spi mode.
? 2010 microchip technology inc. preliminary ds41418a-page 167 pic16f707/pic16lf707 19.2 i 2 c mode the ssp module, in i 2 c mode, implements all slave functions, except general call support. it provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. the ssp module implements the i 2 c standard mode specifications: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ? start and stop bit interrupts enabled to support firmware master mode ?address masking two pins are used for data transfer; the scl pin (clock line) and the sda pin (data line). the user must configure the two pin?s data direction bits as inputs in the appropriate tris register. upon enabling i 2 c mode, the i 2 c slew rate limiters in the i/o pads are controlled by the smp bit of the sspstat register. the ssp module functions are enabled by setting the sspen bit of the sspcon register. data is sampled on the rising edge and shifted out on the falling edge of the clock. this ensures that the sda signal is valid during the scl high time. the scl clock input must have minimum high and low times for proper operation. refer to section 25.0 ?electrical specifications? . figure 19-7: i 2 c? mode block diagram figure 19-8: typical i 2 c? connections the ssp module has six registers for i 2 c operation. they are: ? ssp control (sspcon) register ? ssp status (sspstat) register ? serial receive/transmit buffer (sspbuf) register ? ssp shift register (sspsr), not directly accessible ? ssp address (sspadd) register ? ssp address mask (sspmsk) register 19.2.1 hardware setup selection of i 2 c mode, with the sspen bit of the sspcon register set, forces the scl and sda pins to be open drain, provided these pins are programmed as inputs by setting the appropriate trisc bits. the ssp module will override the input state with the output data, when required, such as for acknowledge and slave-transmitter sequences. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match scl sda shift clock msb lsb sspmsk reg note: pull-up resistors must be provided externally to the scl and sda pins for proper operation of the i 2 c module. slave 1 master sda scl v dd v dd sda scl slave 2 sda scl (optional)
pic16f707/pic16lf707 ds41418a-page 168 preliminary ? 2010 microchip technology inc. 19.2.2 start and stop conditions during times of no data transfer (idle time), both the clock line (scl) and the data line (sda) are pulled high through external pull-up resistors. the start and stop conditions determine the start and stop of data trans- mission. the start condition is defined as a high-to-low transition of the sda line while scl is high. the stop condition is defined as a low-to-high transition of the sda line while scl is high. figure 19-9 shows the start and stop conditions. a master device generates these conditions for starting and terminating data transfer. due to the definition of the start and stop conditions, when data is being trans- mitted, the sda line can only change state when the scl line is low. figure 19-9: start and stop conditions 19.2.3 acknowledge after the valid reception of an address or data byte, the hardware automatically will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to generate this ack pulse. they include any or all of the following: ? the buffer full bit, bf of the sspstat register, was set before the transfer was received. ? the ssp overflow bit, sspov of the sspcon register, was set before the transfer was received. ? the ssp module is being operated in firmware master mode. in such a case, the sspsr register value is not loaded into the sspbuf, but bit sspif of the pir1 register is set. table 19-2 shows the results of when a data transfer byte is received, given the status of bits bf and sspov. flag bit bf is cleared by reading the sspbuf register, while bit sspov is cleared through software. sda scl p stop condition s start condition change of data allowed change of data allowed table 19-2: data transfer received byte actions status bits as data transfer is received sspsr ? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 10 no no yes 11 no no yes 0 1 no no yes note: shaded cells show the conditions where the user software did not properly clear the overflow condition.
? 2010 microchip technology inc. preliminary ds41418a-page 169 pic16f707/pic16lf707 19.2.4 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock line (scl). 19.2.4.1 7-bit addressing in 7-bit addressing mode (figure 19-10), the value of register sspsr<7:1> is compared to the value of register sspadd<7:1>. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: ? the sspsr register value is loaded into the sspbuf register. ? the bf bit is set. ?an ack pulse is generated. ? ssp interrupt flag bit, sspif of the pir1 register, is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. 19.2.4.2 10-bit addressing in 10-bit address mode, two address bytes need to be received by the slave (figure 19-11). the five most sig- nificant bits (msbs) of the first address byte specify if it is a 10-bit address. the r/w bit of the sspstat regis- ter must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 1111 0 a9 a8 0 ?, where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows for reception: 1. load sspadd register with high byte of address. 2. receive first (high) byte of address (bits sspif, bf and ua of the sspstat register are set). 3. read the sspbuf register (clears bit bf). 4. clear the sspif flag bit. 5. update the sspadd register with second (low) byte of address (clears ua bit and releases the scl line). 6. receive low byte of address (bits sspif, bf and ua are set). 7. update the sspadd register with the high byte of address. if match releases scl line, this will clear bit ua. 8. read the sspbuf register (clears bit bf). 9. clear flag bit sspif. if data is requested by the master, once the slave has been addressed: 1. receive repeated start condition. 2. receive repeat of high byte address with r/w = 1 , indicating a read. 3. bf bit is set and the ckp bit is cleared, stopping scl and indicating a read request. 4. sspbuf is written, setting bf, with the data to send to the master device. 5. ckp is set in software, releasing the scl line. 19.2.4.3 address masking the address masking register (sspmsk) is only accessible while the sspm bits of the sspcon register are set to ? 1001 ?. in this register, the user can select which bits of a received address the hardware will compare when determining an address match. any bit that is set to a zero in the sspmsk register, the corresponding bit in the received address byte and sspadd register are ignored when determining an address match. by default, the register is set to all ones, requiring a complete match of a 7-bit address or the lower eight bits of a 10-bit address.
pic16f707/pic16lf707 ds41418a-page 170 preliminary ? 2010 microchip technology inc. 19.2.5 reception when the r/w bit of the received address byte is clear, the master will write data to the slave. if an address match occurs, the received address is loaded into the sspbuf register. an address byte overflow will occur if that loaded address is not read from the sspbuf before the next complete byte is received. an ssp interrupt is generated for each data transfer byte. the bf, r/w and d/a bits of the sspstat register are used to determine the status of the last received byte. figure 19-10: i 2 c? waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 1 2 34 56 78 9123 4 567 89 12 34 bus master sends stop condition bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 receiving address sspif bf sspov ack ack is not sent.
? 2010 microchip technology inc. preliminary ds41418a-page 171 pic16f707/pic16lf707 figure 19-11: i 2 c? slave mode timing (reception, 10-bit address) sspif bf receive data byte r/w receive first byte of address cleared in software cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ckp receive data byte bus master sends stop condition ack cleared in software cleared in software sspov sspov is set because sspbuf is still full. ack is not sent. clock is held low until update of sspadd has taken place sda scl s 12345 6 789 123 4567 89 12345 78 9 p 1111 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d1 d0 ack ack d2 6 ack 1 23 4 5789 d7 d6 d5 d4 d3 d1 d0 d2 6 ack 0
pic16f707/pic16lf707 ds41418a-page 172 preliminary ? 2010 microchip technology inc. 19.2.6 transmission when the r/w bit of the received address byte is set and an address match occurs, the r/w bit of the sspstat register is set and the slave will respond to the master by reading out data. after the address match, an ack pulse is generated by the slave hardware and the scl pin is held low (clock is automatically stretched) until the slave is ready to respond. see section 19.2.7 ?clock stretching? . the data the slave will transmit must be loaded into the sspbuf register, which sets the bf bit. the scl line is released by setting the ckp bit of the sspcon register. an ssp interrupt is generated for each transferred data byte. the sspif flag bit of the pir1 register initiates an ssp interrupt, and must be cleared by software before the next byte is transmitted. the bf bit of the sspstat register is cleared on the falling edge of the 8th received clock pulse. the sspif flag bit is set on the falling edge of the ninth clock pulse. following the 8th falling clock edge, control of the sda line is released back to the master so that the master can acknowledge or not acknowledge the response. if the master sends a not acknowledge, the slave?s transmission is complete and the slave must monitor for the next start condition. if the master acknowledges, control of the bus is returned to the slave to transmit another byte of data. just as with the previous byte, the clock is stretched by the slave, data must be loaded into the sspbuf and ckp must be set to release the clock line (scl). figure 19-12: i 2 c? waveforms for transmission (7-bit address) sda scl sspif bf ckp a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w receiving address 123456789 123456789 p cleared in software set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set) dummy read of sspbuf to clear bf flag sspbuf is written in software from ssp interrupt service routine
? 2010 microchip technology inc. preliminary ds41418a-page 173 pic16f707/pic16lf707 figure 19-13: i 2 c? slave mode timing (transmission 10-bit address) sda scl sspif bf s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 11110 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 11110 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master sends stop condition a9 6 receive second byte of address cleared by hardware when sspadd is updated with low byte of address. ua clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf cleared in software completion of clears bf flag ckp ckp is set in software, initiates transmission ckp is automatically cleared in hardware holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? bus master sends restarts condition dummy read of sspbuf to clear bf flag
pic16f707/pic16lf707 ds41418a-page 174 preliminary ? 2010 microchip technology inc. 19.2.7 clock stretching during any scl low phase, any device on the i 2 c bus may hold the scl line low and delay, or pause, the transmission of data. this ?stretching? of a transmission allows devices to slow down communication on the bus. the scl line must be constantly sampled by the master to ensure that all devices on the bus have released scl for more data. stretching usually occurs after an ack bit of a transmission, delaying the first bit of the next byte. the ssp module hardware automatically stretches for two conditions: ? after a 10-bit address byte is received (update sspadd register) ? anytime the ckp bit of the sspcon register is cleared by hardware the module will hold scl low until the ckp bit is set. this allows the user slave software to update sspbuf with data that may not be readily available. in 10-bit addressing modes, the sspadd register must be updated after receiving the first and second address bytes. the ssp module will hold the scl line low until the sspadd has a byte written to it. the ua bit of the sspstat register will be set, along with sspif, indicating an address update is needed. 19.2.8 firmware master mode master mode of operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits of the sspstat register are cleared from a reset or when the ssp module is disabled (sspen cleared). the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit is set or the bus is idle and both the s and p bits are clear. in firmware master mode, the scl and sda lines are manipulated by setting/clearing the corresponding tris bit(s). the output level is always low, irrespective of the value(s) in the corresponding port register bit(s). when transmitting a ? 1 ?, the tris bit must be set (input) and a ? 0 ?, the tris bit must be clear (output). the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt will occur if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received firmware master mode of operation can be done with either the slave mode idle (sspm<3:0> = 1011 ), or with either of the slave modes in which interrupts are enabled. when both master and slave functionality is enabled, the software needs to differentiate the source(s) of the interrupt. refer to application note an554, ? software implementation of i 2 c? bus master ? (ds00554) for more information. 19.2.9 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allow the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit of the sspstat register is set or when the bus is idle, and both the s and p bits are clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set tris bits). there are two stages where this arbitration of the bus can be lost. they are the address transfer and data transfer stages. when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address transfer stage, communication to the device may be in progress. if addressed, an ack pulse will be generated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. refer to application note an578, ? use of the ssp module in the i 2 c? multi-master environment ? (ds00578) for more information.
? 2010 microchip technology inc. preliminary ds41418a-page 175 pic16f707/pic16lf707 19.2.10 clock synchronization when the ckp bit is cleared, the scl output is held low once it is sampled low. therefore, the ckp bit will not stretch the scl line until an external i 2 c master device has already asserted the scl line low. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (figure 19-14). 19.2.11 sleep operation while in sleep mode, the i 2 c module can receive addresses of data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if ssp interrupt is enabled). figure 19-14: clock synchronization timing sda scl dx-1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon ckp master device deasserts clock master device asserts clock
pic16f707/pic16lf707 ds41418a-page 176 preliminary ? 2010 microchip technology inc. register 19-3: sspcon: synchronous se rial port control register (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive overflow indicator bit 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5 sspen : synchronous serial port enable bit 1 = enables the serial port and configures the sda and scl pins as serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp : clock polarity select bit 1 = release control of scl 0 = holds clock low (clock stretch). (used to ensure data setup time.) bit 3-0 sspm<3:0> : synchronous serial port mode select bits 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = reserved 1001 = load sspmsk register at sspadd sfr address (1) 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled note 1: when this mode is selected, any reads or writes to the sspadd sfr address accesses the sspmsk register. 2: when enabled, these pins must be properly configured as input or output using the associated tris bit.
? 2010 microchip technology inc. preliminary ds41418a-page 177 pic16f707/pic16lf707 register 19-4: sspstat: synchronous serial port status register (i 2 c mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp : spi data input sample phase bit 1 = slew rate control (limiting) disabled. operating in i 2 c standard mode (100 khz and 1 mhz). 0 = slew rate control (limiting) enabled. operating in i 2 c fast mode (400 khz). bit 6 cke : spi clock edge select bit this bit must be maintained clear. used in spi mode only. bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p : stop bit this bit is cleared when the ssp module is disabled, or when the start bit is detected last. 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s : start bit this bit is cleared when the ssp module is disabled, or when the stop bit is detected last. 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or ack bit. 1 = read 0 = write bit 1 ua : update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf : buffer full status bit receive: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit: 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty
pic16f707/pic16lf707 ds41418a-page 178 preliminary ? 2010 microchip technology inc. register 19-5: sspmsk: ssp mask register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspadd to detect i 2 c address match 0 = the received address bit n is not used to detect i 2 c address match bit 0 msk<0>: mask bit for i 2 c slave mode, 10-bit address i 2 c slave mode, 10-bit address (sspm<3:0> = 0111 ): 1 = the received address bit ? 0 ? is compared to sspadd<0> to detect i 2 c address match 0 = the received address bit ? 0 ? is not used to detect i 2 c address match all other ssp modes: this bit has no effect. register 19-6: sspadd: ssp i 2 c? address register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 add7 add6 add5 add4 add3 add2 add1 add0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 add<7:0>: address bits received address table 19-3: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspmsk (2) synchronous serial port (i 2 c mode) address mask register 1111 1111 1111 1111 sspstat smp (1) cke (1) d/a psr/w ua bf 0000 0000 0000 0000 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by ssp module in i 2 c mode. note 1: maintain these bits clear in i 2 c mode. 2: accessible only when sspm<3:0> = 1001 .
? 2010 microchip technology inc. preliminary ds41418a-page 179 pic16f707/pic16lf707 20.0 program memory read the flash program memory is readable during normal operation over the full v dd range of the device. to read data from program memory, five special function registers (sfrs) are used: ?pmcon1 ?pmdatl ?pmdath ? pmadrl ? pmadrh the value written to the pmadrh:pmadrl register pair determines which program memory location is read. the read operation will be initiated by setting the rd bit of the pmcon1 register. the program memory flash controller takes two instructions to complete the read. as a consequence, after the rd bit has been set, the next two instructions will be ignored. to avoid conflict with program execution, it is recommended that the two instructions following the setting of the rd bit are nop . when the read completes, the result is placed in the pmdatlh:pmdatl register pair. refer to example 20-1 for sample code. example 20-1: program memory read note: code-protect does not effect the cpu from performing a read operation on the program memory. for more information, refer to section 8.2 ?code protection? banksel pmadrl ; movf ms_prog_addr, w ; movwf pmadrh ;ms byte of program address to read movf ls_prog_addr, w ; movwf pmadrl ;ls byte of program address to read banksel pmcon1 ; bsf pmcon1, rd ;initiate read nop nop ;any instructions here are ignored as program ;memory is read in second cycle after bsf banksel pmdatl ; movf pmdatl, w ;w = ls byte of program memory read movwf lowpmbyte ; movf pmdath, w ;w = ms byte of program memory read movwf highpmbyte ; required sequence
pic16f707/pic16lf707 ds41418a-page 180 preliminary ? 2010 microchip technology inc. register 20-1: pmcon1: progra m memory control 1 register u-1 u-0 u-0 u-0 u-0 u-0 u-0 r/s-0 ? ? ? ? ? ? ?rd bit 7 bit 0 legend: s = setable bit, cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 1 ? bit 6-1 unimplemented: read as ? 0 ? bit 0 rd: read control bit 1 = initiates a program memory read (the rd is cleared in hardware; the rd bit can only be set (not cleared) in software). 0 = does not initiate a program memory read register 20-2: pmdath: program memory data high register u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? pmd13 pmd12 pmd11 pmd10 pmd9 pmd8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pmd<13:8>: the value of the program memory word pointed to by pmadrh and pmadrl after a program memory read command. register 20-3: pmdatl: program memory data low register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pmd7 pmd6 pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 pmd<7:0>: the value of the program memory word pointed to by pmadrh and pmadrl after a program memory read command.
? 2010 microchip technology inc. preliminary ds41418a-page 181 pic16f707/pic16lf707 register 20-4: pmadrh: program memory address high register u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? pma12 pma11 pma10 pma9 pma8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4-0 pma<12:8>: program memory read address bits register 20-5: pmadrl: program memory address low register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pma7 pma6 pma5 pma4 pma3 pma2 pma1 pma0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 pma<7:0>: program memory read address bits table 20-1: summary of registers as sociated with program memory read name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets pmcon1 ? ? ? ? ? ? ?rd 1--- ---0 1--- ---0 pmadrh ? ? ? program memory read address register high byte ---x xxxx ---x xxxx pmadrl program memory read address register low byte xxxx xxxx xxxx xxxx pmdath ? ? program memory read data register high byte --xx xxxx --xx xxxx pmdatl program memory read data register low byte xxxx xxxx xxxx xxxx legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the program memory read.
pic16f707/pic16lf707 ds41418a-page 182 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 183 pic16f707/pic16lf707 21.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. timer1/3 oscillator is unaffected and peripherals that operate from it may continue operation in sleep. 7. adc is unaffected, if the dedicated frc clock is selected. 8. capacitive sensing oscillators are unaffected. 9. i/o ports maintain the status they had before sleep was executed (driving high, low or high- impedance). 10. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following conditions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using 31 khz lfintosc ? modules using timer1/3 oscillator i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching cur- rents caused by floating inputs. examples of internal circuitry that might be sourcing current include modules such as the dac and fvr modules. see section 11.0 ?digital-to-analog con- verter (dac) module? and section 10.0 ?fixed volt- age reference? for more information on these modules. 21.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running during sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of program execution. when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up.
pic16f707/pic16lf707 ds41418a-page 184 preliminary ? 2010 microchip technology inc. 21.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop . - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction - sleep instruction will be completely exe- cuted - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 21-1: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (3) pc + 2 note 1: xt, hs or lp oscillator mode assumed. 2: clkout is not available in xt, hs, or lp oscillator modes, but shown here for timing reference. 3: t ost = 1024 t osc (drawing not to scale). this delay applies only to xt, hs or lp oscillator modes. 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. table 21-1: summary of registers associated with power-down mode name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 000x 0000 000x iocbf iocbf7 iocbf6 iocbf5 iocbf 4iocbf3iocbf2i ocbf1 iocbf0 0000 0000 0000 0000 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 pie2 tmr3gie tmr3ie tmrbie tmraie ? ? ? ccp2ie 0000 ---0 0000 ---0 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pir2 tmr3gif tmr3if tmrbif tmraif ? ? ? ccp2if 0000 ---0 0000 ---0 status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used in power-down mode.
? 2010 microchip technology inc. preliminary ds41418a-page 185 pic16f707/pic16lf707 22.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: ? icspclk ? icspdat ?mclr /v pp ?v dd ?v ss the device is placed into program/verify mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp from 0v to v pp . in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirectional i/o used for transferring the serial data and the iscpclk pin is the clock input. for more information on icsp? refer to the ? pic16f707/pic16lf707 programming specification? (ds41405a). figure 22-1: typical connect ion for icsp? programming note: the icd 2 produces a v pp voltage greater than the maximum v pp specification of the pic16f707/pic16lf707. when using this programmer, an external circuit, such as the ac164112 mplab ? icd 2 v pp volt- age limiter, is required to keep the v pp voltage within the device specifications. v dd v pp gnd external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). 10k programming signals programmed v dd
pic16f707/pic16lf707 ds41418a-page 186 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 187 pic16f707/pic16lf707 23.0 instruction set summary the pic16f707/pic16lf707 instruction set is highly orthogonal and is comprised of three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the formats for each of the categories is presented in figure 23-1, while the various opcode fields are summarized in table 23-1. table 23-2 lists the instructions recognized by the mpasm tm assembler. for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator, which selects the bit affected by the operation, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an 8-bit or 11-bit constant, or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution time of 1 ? s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 23.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a clrf portb instruction will read portb, clear all the data bits, then write the result back to portb. this example would have the unin- tended consequence of clearing the condition that set the rbif flag. table 23-1: opcode field descriptions figure 23-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f707/pic16lf707 ds41418a-page 188 preliminary ? 2010 microchip technology inc. table 23-2: pic16f707/pic16lf707 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z z z z c c c, dc, z z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k ? k k k ? k ? ? k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c, dc, z z to , pd z to , pd c, dc, z z note 1: when an i/o register is modified as a function of itself (e.g., movf porta, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop .
? 2010 microchip technology inc. preliminary ds41418a-page 189 pic16f707/pic16lf707 23.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction.
pic16f707/pic16lf707 ds41418a-page 190 preliminary ? 2010 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction. call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2010 microchip technology inc. preliminary ds41418a-page 191 pic16f707/pic16lf707 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
pic16f707/pic16lf707 ds41418a-page 192 preliminary ? 2010 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 , destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w= value in fsr register z= 1 movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w= 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movw f option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop
? 2010 microchip technology inc. preliminary ds41418a-page 193 pic16f707/pic16lf707 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction.
pic16f707/pic16lf707 ds41418a-page 194 preliminary ? 2010 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. register f c register f c sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0>
? 2010 microchip technology inc. preliminary ds41418a-page 195 pic16f707/pic16lf707 subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0> xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16f707/pic16lf707 ds41418a-page 196 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 197 pic16f707/pic16lf707 24.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 24.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic16f707/pic16lf707 ds41418a-page 198 preliminary ? 2010 microchip technology inc. 24.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 24.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 24.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 24.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 24.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2010 microchip technology inc. preliminary ds41418a-page 199 pic16f707/pic16lf707 24.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 24.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. 24.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 24.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic16f707/pic16lf707 ds41418a-page 200 preliminary ? 2010 microchip technology inc. 24.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 24.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 24.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
? 2010 microchip technology inc. preliminary ds41418a-page 201 pic16f707/pic16lf707 25.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss , pic16f707 ............................................................................... -0.3v to +6.5v voltage on v cap pin with respect to v ss , pic16f707 ....................................................................... -0.3v to +4.0v voltage on v dd with respect to v ss , pic16lf707 ............................................................................. -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin ...................................................................................................................... 95 m a maximum current into v dd pin ......................................................................................................................... 7 0 ma clamp current, i k (v pin < 0 or v pin > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma maximum current sunk by all ports (2) , -40c ? t a ? +85c for industrial ........................................................ 200 ma maximum current sunk by all ports (2) , -40c ? t a ? +125c for extended........................................................ 90 ma maximum current sourced by all ports (2) , 40c ? t a ? +85c for industrial ................................................... 140 ma maximum current sourced by all ports (2) , -40c ? t a ? +125c for extended................................................... 65 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability.
pic16f707/pic16lf707 ds41418a-page 202 preliminary ? 2010 microchip technology inc. 25.1 dc characteristics: pic16f707/pic16lf707-i/e (industrial, extended) pic16lf707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage pic16lf707 1.8 1.8 2.3 2.5 ? ? ? ? 3.6 3.6 3.6 3.6 v v v v f osc ? 16 mhz: hfintosc, ec f osc ? 4mhz f osc ? 20 mhz, ec f osc ? 20 mhz, hs d001 pic16f707 1.8 1.8 2.3 2.5 ? ? ? ? 5.5 5.5 5.5 5.5 v v v v f osc ? 16 mhz: hfintosc, ec f osc ? 4 mhz f osc ? 20 mhz, ec f osc ? 20 mhz, hs d002* v dr ram data retention voltage (1) pic16lf707 1.5 ? ? v device in sleep mode d002* pic16f707 1.7 ? ? v device in sleep mode v por * power-on reset release voltage ?1.6? v v porr * power-on reset rearm voltage pic16lf707 ? 0.8 ? v device in sleep mode pic16f707 ? 1.7 ? v device in sleep mode d003 v fvr fixed voltage reference voltage, initial accuracy -5.5 -5.5 -5.5 ? ? ? 5.5 5.5 5.5 % % % v fvr = 1.024v, v dd ? 2.5v v fvr = 2.048v, v dd ? 2.5v v fvr = 4.096v, v dd ?? 4.75v; -40 ?? t a ??? 85c -6 -6 -6 ? ? ? 6 6 6 % % % v fvr = 1.024v, v dd ? 2.5v v fvr = 2.048v, v dd ? 2.5v v fvr = 4.096v, v dd ?? 4.75v; -40 ?? t a ??? 125c d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 3.2 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
? 2010 microchip technology inc. preliminary ds41418a-page 203 pic16f707/pic16lf707 figure 25-1: por and por rearm with slow rising v dd v dd v por v porr v ss v ss npor t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2)
pic16f707/pic16lf707 ds41418a-page 204 preliminary ? 2010 microchip technology inc. 25.2 dc characteristics: pic16f707/pic16lf707-i/e (industrial, extended) pic16lf707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d009 ldo regulator ? 350 ? ? a ? hs, ec or intosc/intoscio (8-16 mh z ) clock modes with all v cap pins disabled ? 50 ? ? a ? all v cap pins disabled ? 30 ? ? a ? v cap enabled on ra0, ra5 or ra6 ? 5 ? ? a ? lp clock mode and sleep (requires fvr and bor to be disabled) d010 ? 7.0 12 ? a1.8f osc = 32 khz lp oscillator mode (note 4) , -40c ? t a ? +85c ?9.0 14 ? a3.0 d010 ? 11 20 ? a 1.8 f osc = 32 khz lp oscillator mode (note 4) , -40c ? t a ? +85c ? 14 22 ? a 3.0 ? 15 24 ? a 5.0 d011 ? 7.0 12 ? a1.8 f osc = 32 khz lp oscillator mode -40c ? t a ? +125c ?9.0 18 ? a3.0 d011 ? 11 21 ? a 1.8 f osc = 32 khz lp oscillator mode (note 4) -40c ? t a ? +125c ? 14 25 ? a 3.0 ? 15 27 ? a 5.0 d011 ? 110 150 ? a1.8f osc = 1 mhz xt oscillator mode ? 150 215 ? a3.0 d011 ? 120 175 ? a 1.8 f osc = 1 mhz xt oscillator mode (note 5) ? 180 250 ? a 3.0 ? 240 300 ? a 5.0 d012 ? 230 300 ? a1.8f osc = 4 mhz xt oscillator mode ? 400 600 ? a3.0 d012 ? 250 350 ? a 1.8 f osc = 4 mhz xt oscillator mode (note 5) ? 420 650 ? a 3.0 ? 500 750 ? a 5.0 d013 ? 125 180 ? a1.8f osc = 1 mhz ec oscillator mode ? 230 270 ? a3.0 d013 ? 150 205 ? a 1.8 f osc = 1 mhz ec oscillator mode (note 5) ? 225 320 ? a 3.0 ? 250 410 ? a 5.0 note 1: the test conditions for all i dd measurements in active operation mode ar e: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pa ttern and temperature, also have an impact on the current consumption. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ?? 4: fvr and bor are disabled. 5: 0.1 ? f capacitor on v cap (ra0).
? 2010 microchip technology inc. preliminary ds41418a-page 205 pic16f707/pic16lf707 supply current (i dd ) (1, 2) d014 ? 290 330 ? a1.8f osc = 4 mhz ec oscillator mode ? 460 500 ? a3.0 d014 ? 300 430 ? a 1.8 f osc = 4 mhz ec oscillator mode (note 5) ? 450 655 ? a 3.0 ? 500 730 ? a 5.0 d015 ? 100 130 ? a1.8f osc = 500 khz mfintosc mode ? 120 150 ? a3.0 d015 ? 115 195 ? a 1.8 f osc = 500 khz mfintosc mode (note 5) ? 135 200 ? a 3.0 ? 150 220 ? a 5.0 d016 ? 650 800 ? a1.8f osc = 8 mhz hfintosc mode ? 1000 1200 ? a3.0 d016 ? 625 850 ? a 1.8 f osc = 8 mhz hfintosc mode (note 5) ? 1000 1200 ? a 3.0 ? 1100 1500 ? a 5.0 d017 ? 1.0 1.2 ma 1.8 f osc = 16 mhz hfintosc mode ? 1.5 1.85 ma 3.0 d017 ? 1 1.2 ma 1.8 f osc = 16 mhz hfintosc mode (note 5) ? 1.5 1.7 ma 3.0 ? 1.7 2.1 ma 5.0 d018 ? 210 240 ? a1.8f osc = 4 mhz extrc mode (note 3, note 5) ? 340 380 ? a3.0 d018 ? 225 320 ? a 1.8 f osc = 4 mhz extrc mode (note 3, note 5) ? 360 445 ? a 3.0 ? 410 650 ? a 5.0 d019 ? 1.6 1.9 ma 3.0 f osc = 20 mhz hs oscillator mode ?2.02.8ma 3.6 d019 ? 1.6 2 ma 3.0 f osc = 20 mhz hs oscillator mode (note 5) ? 1.9 3.2 ma 5.0 25.2 dc characteristics: pic16f707/pic16lf707-i/e (industrial, extended) (continued) pic16lf707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pa ttern and temperature, also have an impact on the current consumption. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ?? 4: fvr and bor are disabled. 5: 0.1 ? f capacitor on v cap (ra0).
pic16f707/pic16lf707 ds41418a-page 206 preliminary ? 2010 microchip technology inc. 25.3 dc characteristics: pic16f707/pic16lf707-i/e (power-down) pic16lf707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note power-down base current (i pd ) (2) d020 ? 0.02 0.7 3.9 ? a 1.8 wdt, bor, fvr, and t1osc disabled, all peripherals inactive ? 0.08 1.0 4.3 ? a3.0 d020 ? 4.3 10.2 17 ? a 1.8 wdt, bor, fvr, and t1osc disabled, all peripherals inactive ? 5 10.5 18 ? a 3.0 ? 5.5 11.8 21 ? a 5.0 d021 ? 0.5 1.7 4.1 ? a 1.8 lpwdt current (note 1) ? 0.8 2.5 4.8 ? a3.0 d021 ? 6 13.5 16.4 ? a 1.8 lpwdt current (note 1) ? 6.5 14.5 16.8 ? a 3.0 ? 7.5 16 18.7 ? a 5.0 d021a ? 8.5 18 22 ? a 1.8 fvr current (note 1, note 3) ? 8.5 18 22 ? a3.0 d021a ? 23 44 48 ? a 1.8 fvr current (note 1, note 3, note 5) ? 25 45 55 ? a 3.0 ? 26 60 70 ? a 5.0 d022 ? ? ? ? ? a 1.8 bor current (note 1, note 3) ? 7.5 12 22 ? a3.0 d022 ? ? ? ? ? a 1.8 bor current (note 1, note 3, note 5) ? 23 42 49 ? a 3.0 ? 25 46 50 ? a 5.0 d026 ? 0.6 3 7 ? a 1.8 t1osc current (note 1) ?1.8 6 8.75 ? a3.0 d026 ? 4.5 11.1 ? ? a 1.8 t1osc current (note 1) ? 6 12.5 ? ? a 3.0 ? 7 13.5 ? ? a 5.0 ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: fixed voltage reference is automatic ally enabled whenever the bor is enabled. 4: a/d oscillator source is f rc . 5: 0.1 ? f capacitor on v cap (ra0). 6: includes fvr ipd and dac ipd.
? 2010 microchip technology inc. preliminary ds41418a-page 207 pic16f707/pic16lf707 power-down base current (i pd ) (2) d027 ? 0.06 0.7 5.0 ? a 1.8 a/d current (note 1, note 4) , no conversion in progress ? 0.08 1.0 5.5 ? a3.0 d027 ? 6 10.7 18 ? a 1.8 a/d current (note 1, note 4) , no conversion in progress ? 7 10.6 20 ? a 3.0 ? 7.2 11.9 22 ? a 5.0 d027a ? 250 400 ? ? a 1.8 a/d current (note 1, note 4) , conversion in progress ? 250 400 ? ? a3.0 d027a ? 280 430 ? ? a 1.8 a/d current (note 1, note 4, note 5) , conversion in progress ? 280 430 ? ? a 3.0 ? 280 430 ? ? a 5.0 d028 ? 2.2 3.2 14.4 ? a 1.8 cap sense low range low power ?3.34.415.6 ? a3.0 d028 ? 6.5 13 21 ? a 1.8 cap sense low range low power ? 8 14 23 ? a 3.0 ? 8 14 25 ? a 5.0 d028a ? 4.2 6 17 ? a 1.8 cap sense low range medium power ?6 7 18 ? a3.0 d028a ? 8.5 15.5 23 ? a 1.8 cap sense low range medium power ? 11 17 24 ? a 3.0 ? 11 18 27 ? a 5.0 d028b ? 12 14 25 ? a 1.8 cap sense low range high power ?32 35 44 ? a3.0 d028b ? 16 20 31 ? a 1.8 cap sense low range high power ? 36 41 50 ? a 3.0 ? 42 49 58 ? a 5.0 d028c ? 115 ? ? ? a 1.8 cap sense highrange low power (note 6) ?120 ? ? ? a3.0 d028c ? 135 ? ? ? a 1.8 cap sense high range low power (note 6) ? 140 ? ? ? a 3.0 ? 150 ? ? ? a 5.0 d028d ? 125 ? ? ? a 1.8 cap sense highrange medium power (note 6) ?130 ? ? ? a3.0 25.3 dc characteristics: pic16f707/pic16lf707-i/e (power-down) (continued) pic16lf707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: fixed voltage reference is automatic ally enabled whenever the bor is enabled. 4: a/d oscillator source is f rc . 5: 0.1 ? f capacitor on v cap (ra0). 6: includes fvr ipd and dac ipd.
pic16f707/pic16lf707 ds41418a-page 208 preliminary ? 2010 microchip technology inc. d028d ? 145 ? ? ? a 1.8 cap sense high range medium power (note 6) ? 150 ? ? ? a 3.0 ? 160 ? ? ? a 5.0 d028e ? 150 ? ? ? a 1.8 cap sense highrange high power (note 6) ?170 ? ? ? a3.0 d028e ? 180 ? ? ? a 1.8 cap sense high range high power (note 6) ? 190 ? ? ? a 3.0 ? 200 ? ? ? a 5.0 25.3 dc characteristics: pic16f707/pic16lf707-i/e (power-down) (continued) pic16lf707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f707 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: fixed voltage reference is automatic ally enabled whenever the bor is enabled. 4: a/d oscillator source is f rc . 5: 0.1 ? f capacitor on v cap (ra0). 6: includes fvr ipd and dac ipd.
? 2010 microchip technology inc. preliminary ds41418a-page 209 pic16f707/pic16lf707 25.4 dc characteristics: pic16f707/pic16lf707-i/e dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030 with ttl buffer ? ? 0.8 v 4.5v ? v dd ? 5.5v d030a ? ? 0.15 v dd v1.8v ? v dd ? 4.5v d031 with schmitt trigger buffer ? ? 0.2 v dd v2.0v ? v dd ? 5.5v with i 2 c? levels ? ? 0.3 v dd v d032 mclr , osc1 (rc mode) (1) ??0.2v dd v d033a osc1 (hs mode) ? ? 0.3 v dd v v ih input high voltage i/o ports: ? ? d040 with ttl buffer 2.0 ? ? v 4.5v ? v dd ?? 5.5v d040a 0.25 v dd + 0.8 ??v1.8v ? v dd ? 4.5v d041 with schmitt trigger buffer 0.8 v dd ??v2.0v ? v dd ? 5.5v with i 2 c? levels 0.7 v dd ??v d042 mclr 0.8 v dd ??v d043a osc1 (hs mode) 0.7 v dd ??v d043b osc1 (rc mode) 0.9 v dd ??v (note 1) i il input leakage current (2) d060 i/o ports ? 5 5 125 1000 na na v ss ? v pin ? v dd , pin at high- impedance, 85c 125c d061 mclr (3) ? 50 200nav ss ? v pin ? v dd , 85c i pur portb weak pull-up current d070* 25 25 100 140 200 300 ? a v dd = 3.3v, v pin = v ss v dd = 5.0v, v pin = v ss v ol output low voltage (4) d080 i/o ports ??0.6v i ol = 8ma, v dd = 5v i ol = 6ma, v dd = 3.3v i ol = 1.8ma, v dd = 1.8v v oh output high voltage (4) d090 i/o ports v dd - 0.7 ? ? v i oh = 3.5ma, v dd = 5v i oh = 3ma, v dd = 3.3v i oh = 1ma, v dd = 1.8v capacitive loading specs on output pins d101* cosc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101a* c io all i/o pins ? ? 50 pf program flash memory legend: tbd = to be determined * these parameters are char acterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schm itt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
pic16f707/pic16lf707 ds41418a-page 210 preliminary ? 2010 microchip technology inc. d130 e p cell endurance 100 1k ? e/w temper ature during programming: 10c ? t a ? 40c d131 v dd for read v min ??v voltage on mclr /v pp during erase/program 8.0 ? 9.0 v temperature during programming: 10c ? t a ? 40c v dd for bulk erase 2.7 3 ? v temperature during programming: 10c ? t a ? 40c d132 v pew v dd for write or row erase 2.7 ? ? v v min = minimum operating voltage v max = maximum operating voltage i pppgm current on mclr /v pp during erase/write ??5.0ma temperature during programming: 10c ? t a ? 40c i ddpgm current on v dd during erase/ write ? 5.0 ma temperature during programming: 10c ? t a ? 40c d133 t pew erase/write cycle time ? 2.8 ms temperature during programming: 10c ? t a ? 40c d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated v cap capacitor charging d135 charging current ? 200 ? ? a d135a source/sink capability when charging complete ?0.0?ma 25.4 dc characteristics: pic16f707/pic16lf707-i/e (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions legend: tbd = to be determined * these parameters ar e characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schm itt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
? 2010 microchip technology inc. preliminary ds41418a-page 211 pic16f707/pic16lf707 25.5 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 60 ? c/w 28-pin spdip package 80 ? c/w 28-pin soic package 90 ? c/w 28-pin ssop package 27.5 ? c/w 28-pin uqfn 4x4mm package 27.5 ? c/w 28-pin qfn 6x6mm package 47.2 ? c/w 40-pin pdip package 46 ? c/w 44-pin tqfp package 24.4 ? c/w 44-pin qfn 8x8mm package th02 ? jc thermal resistance junction to case 31.4 ? c/w 28-pin spdip package 24 ? c/w 28-pin soic package 24 ? c/w 28-pin ssop package 24 ? c/w 28-pin uqfn 4x4mm package 24 ? c/w 28-pin qfn 6x6mm package 24.7 ? c/w 40-pin pdip package 14.5 ? c/w 44-pin tqfp package 20 ? c/w 44-pin qfn 8x8mm package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation ? w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature 3: t j = junction temperature
pic16f707/pic16lf707 ds41418a-page 212 preliminary ? 2010 microchip technology inc. 25.6 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 25-2: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins, 15 pf for osc2 output load condition pin
? 2010 microchip technology inc. preliminary ds41418a-page 213 pic16f707/pic16lf707 25.7 ac characteristics: pic16f707-i/e figure 25-3: clock timing figure 25-4: pic16f707 voltag e frequency graph, -40c ? t a ?? +125c osc1/clkin osc2/clkout q4 q1 q2 q3 q4 q1 os02 os03 os04 os04 osc2/clkout (lp,xt,hs modes) (clkout mode) 1.8 2.5 2.0 0 2.3 frequency (mhz) v dd (v) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 25-1 for each oscillator mode?s supported frequencies. 420 10 16 5.5 3.6
pic16f707/pic16lf707 ds41418a-page 214 preliminary ? 2010 microchip technology inc. figure 25-5: pic16lf707 voltage frequency graph, -40c ? t a ?? +125c figure 25-6: hfintosc frequency accuracy over device v dd and temperature 1.8 2.5 2.0 0 2.3 frequency (mhz) v dd (v) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 25-1 for each oscillator mode?s supported frequencies. 420 10 16 3.6 125 25 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.5 3.0 3.5 5.5 1.8 note 1: this chart covers both regulator enabled and regulator disabled states. 2: regulator nominal voltage. 3.3 (2) -40 -20 + 5% 2% + 5% 3%
? 2010 microchip technology inc. preliminary ds41418a-page 215 pic16f707/pic16lf707 table 25-1: clock oscillator timing requirements standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc ? 37 khz lp oscillator mode dc ? 4 mhz xt oscillator mode dc ? 20 mhz hs oscillator mode dc ? 20 mhz ec oscillator mode oscillator frequency (1) ? 32.768 ? khz lp oscillator mode 0.1 ? 4 mhz xt oscillator mode 1 ? 4 mhz hs oscillator mode, v dd ?? 2.7v 1 ? 20 mhz hs oscillator mode, v dd ?? 2.7v dc ? 4 mhz rc oscillator mode os02 t osc external clkin period (1) 27 ? ?? s lp oscillator mode 250 ? ? ns xt oscillator mode 50 ? ? ns hs oscillator mode 50 ? ? ns ec oscillator mode oscillator period (1) ? 30.5 ? ? s lp oscillator mode 250 ? 10,000 ns xt oscillator mode 250 ? 1,000 ns hs oscillator mode, v dd ?? 2.7v 50 ? 1,000 ns hs oscillator mode, v dd ?? 2.7v 250 ? ? ns rc oscillator mode os03 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc os04* tosh, to s l external clkin high, external clkin low 2?? ? s lp oscillator 100 ? ? ns xt oscillator 20 ? ? ns hs oscillator os05* tosr, to s f external clkin rise, external clkin fall 0? ? ns lp oscillator 0? ? ns xt oscillator 0? ? ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time bas e period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an uns table oscillator operation and/o r higher than expected current consumption. all devices are tested to operate at ?min? va lues with an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle ti me limit is ?dc? (no clock) for all devices.
pic16f707/pic16lf707 ds41418a-page 216 preliminary ? 2010 microchip technology inc. figure 25-7: clkout and i/o timing table 25-2: oscillator parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic freq. tolerance min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (2) ? 2% ? 16.0 ? mhz 0c ? t a ? +85c, v dd ????? v ? 5% ? 16.0 ? mhz -40c ? t a ? +125c os08a mf osc internal calibrated mfintosc frequency (2) ? 2% ? 500 ? khz 0c ? t a ? +85c v dd ????? v ? 5% ? 500 10 khz -40c ? t a ? +125c os10* t iosc st hfintosc wake-up from sleep start-up time ??58 ? s mfintosc wake-up from sleep start-up time ? ? 20 30 ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time bas e period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an uns table oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? valu es with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle ti me limit is ?dc? (no clock) for all devices. 2: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. 3: by design. f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle
? 2010 microchip technology inc. preliminary ds41418a-page 217 pic16f707/pic16lf707 table 25-3: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl fosc ? to clkout ? (1) ??70nsv dd = 3.3-5.0v os12 tosh2ckh fosc ? to clkout ? (1) ??72nsv dd = 3.3-5.0v os13 tckl2iov clkout ? to port out valid (1) ??20ns os14 tiov2ckh port input valid before clkout ? (1) t osc + 200 ns ? ? ns os15 tosh2iov fosc ? (q1 cycle) to port out valid ? 50 70* ns v dd = 3.3-5.0v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in hold time) 50 ? ? ns v dd = 3.3-5.0v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ? ? ns os18 tior port output rise time (2) ? ? 40 15 72 32 ns v dd = 2.0v v dd = 3.3-5.0v os19 tiof port output fall time (2) ? ? 28 15 55 30 ns v dd = 2.0v v dd = 3.3-5.0v os20* tinp int pin input high or low time 25 ? ? ns os21* trbp portb interrupt-on-change new input level time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 2: includes osc2 in clkout mode.
pic16f707/pic16lf707 ds41418a-page 218 preliminary ? 2010 microchip technology inc. figure 25-8: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 25-9: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset (1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration word register is programmed to ? 0 ?. 2 ms delay if pwrte = 0 and vregen = 1 . reset (due to bor) v bor and v hyst 37
? 2010 microchip technology inc. preliminary ds41418a-page 219 pic16f707/pic16lf707 table 25-4: reset, watchdog timer, oscill ator start-up timer, power-up timer, and brown-out reset parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc lmclr pulse width (low) 2 5 ? ? ? ? ? s ? s v dd = 3.3-5v, -40c to +85c v dd = 3.3-5v 31 t wdtlp low power watchdog timer time- out period (no prescaler) 10 18 27 ms v dd = 3.3v-5v 32 t ost oscillator start-up timer period (1), (2) ?1024?tosc (note 3) 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage 2.38 1.80 2.5 1.9 2.73 2.11 v borv=2.5v borv=1.9v 36* v hyst brown-out reset hysteresis 0 25 50 mv -40c to +85c 37* t bordc brown-out reset dc response time 135 10 ? sv dd ? v bor , -40c to +85c v dd ? v bor * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: by design. 3: period of the slower clock. 4: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended.
pic16f707/pic16lf707 ds41418a-page 220 preliminary ? 2010 microchip technology inc. figure 25-10: timer0/a/b and timer1/3 external clock timings t0cki/tacki/tbcki t1cki/t3cki 40 41 42 45 46 47 49 tmrx table 25-5: timer0/a/b and timer1/3 external clock requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki/tacki/tbcki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with pres- caler 10 ? ? ns 41* t t 0l t0cki/tacki/tbcki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with pres- caler 10 ? ? ns 42* t t 0p t0cki/tacki/tbcki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki/ t3cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki/ t3cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki/ t3cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns 48 f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) 32.4 32.76 8 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? timers in sync mode * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2010 microchip technology inc. preliminary ds41418a-page 221 pic16f707/pic16lf707 figure 25-11: capture/com pare/pwm timings (ccp) note: refer to figure 25-2 for load conditions. (capture mode) cc01 cc02 cc03 ccpx table 25-6: capture/compare/pwm requirements (ccp) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions cc01* tccl ccpx input low time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc02* tcch ccpx input high time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc03* tccp ccpx input period 3t cy + 40 n ? ? ns n = prescale value (1, 4 or 16) * these parameters are char acterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. table 25-7: pic16f707 a/d co nverter (adc) characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad01 n r resolution ? ? 8 bit ad02 e il integral error ? ? 1.7 lsb v ref = 3.0v ad03 e dl differential error ? ? 1 lsb no missing codes v ref = 3.0v ad04 e off offset error ? ? 2.2 lsb v ref = 3.0v ad05 e gn gain error ? ? 1.5 lsb v ref = 3.0v ad06 v ref reference voltage (3) 1.8 ? v dd v ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 50 k ? can go higher if external 0.01 ? f capacitor is present on input pin. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never dec reases with an increase in the input voltage and has no missing codes. 3: when adc is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the adc module.
pic16f707/pic16lf707 ds41418a-page 222 preliminary ? 2010 microchip technology inc. figure 25-12: pic16f707 a/d conv ersion timing (normal mode) table 25-8: pic16f707 a/d conversion requirements standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad130* t ad a/d clock period 1.0 ? 9.0 ? st osc -based a/d internal rc oscillator period 1.0 2.0 6.0 ? s adcs<1:0> = 11 (adrc mode) ad131 t cnv conversion time (not including acquisition time) (1) ? 10.5 ? t ad set go/done bit to conversion complete ad132* t acq acquisition time ? 1.0 ? ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle. ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 765 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 4 ad134 (t osc /2 (1) ) 1 t cy ad132
? 2010 microchip technology inc. preliminary ds41418a-page 223 pic16f707/pic16lf707 figure 25-13: pic16f707 a/d conv ersion timing (sleep mode) figure 25-14: usart synchronous transmission (master/slave) timing ad132 ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 7 5 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. ad134 4 6 1 t cy (t osc /2 + t cy (1) ) 1 t cy note: refer to figure 25-2 for load conditions. us121 us121 us120 us122 ck dt table 25-9: usart synchronous transmission requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us120 t ck h2 dt v sync xmit (m aster and s lave ) clock high to data-out valid 3.0-5.5v ? 80 ns 1.8-5.5v ? 100 ns us121 t ckrf clock out rise time and fall time (master mode) 3.0-5.5v ? 45 ns 1.8-5.5v ? 50 ns us122 t dtrf data-out rise time and fall time 3.0-5.5v ? 45 ns 1.8-5.5v ? 50 ns
pic16f707/pic16lf707 ds41418a-page 224 preliminary ? 2010 microchip technology inc. figure 25-15: usart synchrono us receive (master/slave) timing figure 25-16: spi master mode timing (cke = 0 , smp = 0 ) note: refer to figure 25-2 for load conditions. us125 us126 ck dt table 25-10: usart synchrono us receive requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us125 t dt v2 ckl sync rcv (m aster and s lave ) data-hold before ck ? (dt hold time) 10 ? ns us126 t ck l2 dtl data-hold after ck ? (dt hold time) 15 ? ns ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 25-2 for load conditions.
? 2010 microchip technology inc. preliminary ds41418a-page 225 pic16f707/pic16lf707 figure 25-17: spi master mode timing (cke = 1 , smp = 1 ) figure 25-18: spi slav e mode timing (cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp81 sp71 sp72 sp74 sp75, sp76 sp78 sp80 msb sp79 sp73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 25-2 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp77 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in sp83 note: refer to figure 25-2 for load conditions.
pic16f707/pic16lf707 ds41418a-page 226 preliminary ? 2010 microchip technology inc. figure 25-19: spi slav e mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp82 sp74 sp75, sp76 msb bit 6 - - - - - -1 lsb sp77 msb in bit 6 - - - -1 lsb in sp80 sp83 note: refer to figure 25-2 for load conditions.
? 2010 microchip technology inc. preliminary ds41418a-page 227 pic16f707/pic16lf707 figure 25-20: i 2 c? bus start/stop bits timing table 25-11: spi mode requirements param no. symbol characteristic min. typ? max. units conditions sp70* t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input t cy ??ns sp71* t sc h sck input high time (slave mode) t cy + 20 ? ? ns sp72* t sc l sck input low time (slave mode) t cy + 20 ? ? ns sp73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ? ns sp74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ? ns sp75* t do r sdo data output rise time 3.0-5.5v ? 10 25 ns 1.8-5.5v ? 25 50 ns sp76* t do f sdo data output fall time ? 10 25 ns sp77* t ss h2 do zss ? to sdo output high-impedance 10 ? 50 ns sp78* t sc r sck output rise time (master mode) 3.0-5.5v ? 10 25 ns 1.8-5.5v ? 25 50 ns sp79* t sc f sck output fall time (master mode) ? 10 25 ns sp80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 3.0-5.5v ? ? 50 ns 1.8-5.5v ? ? 145 ns sp81* t do v2 sc h , t do v2 sc l sdo data output setup to sck edge tcy ? ? ns sp82* t ss l2 do v sdo data output valid after ss ? edge ? ? 50 ns sp83* t sc h2 ss h, t sc l2 ss h ss ?? after sck edge 1.5t cy + 40 ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note : refer to figure 25-2 for load conditions. sp91 sp92 sp93 scl sda start condition stop condition sp90
pic16f707/pic16lf707 ds41418a-page 228 preliminary ? 2010 microchip technology inc. figure 25-21: i 2 c? bus data timing table 25-12: i 2 c? bus start/stop bits requirements param no. symbol characteristic min. typ max. units conditions sp90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? sp91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? sp92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? sp93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested. note: refer to figure 25-2 for load conditions. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 scl sda in sda out
? 2010 microchip technology inc. preliminary ds41418a-page 229 pic16f707/pic16lf707 table 25-13: i 2 c? bus data requirements param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 100 khz mode 4.0 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? sp101* t low clock low time 100 khz mode 4.7 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? sp102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sda and scl fall time 100 khz mode ? 250 ns 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns sp109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns sp110* t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmis- sion can start 400 khz mode 1.3 ? ? s sp111 c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c ? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
pic16f707/pic16lf707 ds41418a-page 230 preliminary ? 2010 microchip technology inc. figure 25-22: cap sense oscillator table 25-14: cap sense os cillator specifications param. no. symbol characteristic min. typ? max. units conditions cs01 i src current source high ? -5.8 -6 ? a -40, -85c medium ? -1.1 -3.2 ? a low ? -0.2 -0.9 ? a cs02 i snk current sink high ? 6.6 6 ? a -40, -85c medium ? 1.3 3.2 ? a low ? 0.24 0.9 ? a cs03 vc hyst cap hysteresis high ? 525 ? mv vc th -vc tl medium ? 375 ? mv low ? 280 ? mv * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. i src vc th vc tl i snk enabled enabled
? 2010 microchip technology inc. preliminary ds41418a-page 231 pic16f707/pic16lf707 26.0 dc and ac characteristics graphs and charts ?typical? represents the mean of the distribution at 25 ? c. ?maximum? or ?minimum? represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where ? is a standard deviation, over the whole temperature range. figure 26-1: pic16f707 maximum i dd vs. f osc over v dd , ec mode, v cap = 0.1f note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 1.8v 2.5v 3v 3.6v 5v 0.00 200.00 400.00 600.00 800.00 1,000.00 1,200.00 1,400.00 1,600.00 1,800.00 2,000.00 2,200.00 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz 20 mhz v dd (v) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a)
pic16f707/pic16lf707 ds41418a-page 232 preliminary ? 2010 microchip technology inc. figure 26-2: pic16lf707 maximum i dd vs. f osc over v dd , ec mode figure 26-3: pic16f707 typical i dd vs. f osc over v dd , ec mode, v cap = 0.1f 1.8v 2v 2.5v 3v 3.3v 3.6v 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2,200 2,400 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) f osc i dd (a) 1.8v 2.5v 3v 3.6v 5v 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) f osc i dd (a)
? 2010 microchip technology inc. preliminary ds41418a-page 233 pic16f707/pic16lf707 figure 26-4: pic16lf707 typical i dd vs. f osc over v dd , ec mode figure 26-5: pic16f707 maximum i dd vs. v dd over f osc , extrc mode, v cap = 0.1f 1.8v 2v 2.5v 3v 3.3v 3.6v 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2,200 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) f osc 1 mhz 4 mhz 0 100 200 300 400 500 600 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 234 preliminary ? 2010 microchip technology inc. figure 26-6: pic16lf707 maximum i dd vs. v dd over f osc , extrc mode figure 26-7: pic16f707 typical i dd vs. v dd over f osc , extrc mode, v cap = 0.1f 1 mhz 4 mhz 0 50 100 150 200 250 300 350 400 450 500 1.8 2 2.5 3 3.3 3.6 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v) 1 mhz 4 mhz 0 50 100 150 200 250 300 350 400 450 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) v dd (v) i dd (a)
? 2010 microchip technology inc. preliminary ds41418a-page 235 pic16f707/pic16lf707 figure 26-8: pic16lf707 typical i dd vs. v dd over f osc , extrc mode figure 26-9: pic16f707 maximum i dd vs. f osc over v dd , hs mode, v cap = 0.1f 1 mhz 4 mhz 0 50 100 150 200 250 300 350 400 450 1.8 2 2.5 3 3.3 3.6 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) v dd (v) i dd (a) 3v 3.6v 4.5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 4 mhz 6 mhz 8 mhz 10 mhz 13 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) fosc i dd (ma) 5v
pic16f707/pic16lf707 ds41418a-page 236 preliminary ? 2010 microchip technology inc. figure 26-10: pic16lf707 maximum i dd vs. f osc over v dd , hs mode figure 26-11: pic16f707 typical i dd vs. f osc over v dd , hs mode, v cap = 0.1f 2.5v 3v 3.6v 0.00 0.50 1.00 1.50 2.00 2.50 4 mhz 6 mhz 8 mhz 10 mhz 13 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) fosc i dd (ma) 3.3v 3v 3.6v 4.5v 0.00 0.50 1.00 1.50 2.00 4 mhz 6 mhz 8 mhz 10 mhz 13 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) fosc i dd (ma) 5v
? 2010 microchip technology inc. preliminary ds41418a-page 237 pic16f707/pic16lf707 figure 26-12: pic16lf707 typical i dd vs. f osc over v dd , hs mode figure 26-13: pic16f707 maximum i dd vs. v dd over f osc , xt mode, v cap = 0.1f 2.5v 3v 3.3v 0.00 0.50 1.00 1.50 2.00 2.50 4 mhz 6 mhz 8 mhz 10 mhz 13 mhz 16 mhz 20 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (ma) fosc 3.6v 1 mhz 4 mhz 0 100 200 300 400 500 600 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 238 preliminary ? 2010 microchip technology inc. figure 26-14: pic16lf707 maximum i dd vs. v dd over f osc , xt mode figure 26-15: pic16f707 typical i dd vs. v dd over f osc , xt mode, v cap = 0.1f 1 mhz 4 mhz 0 100 200 300 400 500 600 1.8 2 2.5 3 3.3 3.6 i dd (a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) v dd (v) 1 mhz 4 mhz 0 100 200 300 400 500 600 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 239 pic16f707/pic16lf707 figure 26-16: pic16lf707 typical i dd vs. v dd over f osc , xt mode figure 26-17: pic16f707 i dd vs. v dd , lp mode, v cap = 0.1f 1 mhz 4 mhz 0 100 200 300 400 500 600 1.8 2 2.5 3 3.3 3.6 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v) 32 khz typical 32 khz maximum 10.0 12.5 15.0 17.5 20.0 1.8 3 5 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v) v dd (v)
pic16f707/pic16lf707 ds41418a-page 240 preliminary ? 2010 microchip technology inc. figure 26-18: pic16lf707 i dd vs. v dd , lp mode figure 26-19: pic16f707 maximum i dd vs. f osc over v dd , intosc mode, v cap = 0.1f 32 khz typical 32 khz maximum 5 10 15 20 25 30 1.8 3 3.3 3.6 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v) 110 120 130 140 150 160 170 180 190 200 210 62.5 khz 125 khz 250 khz 500 khz 5v 3.6v 1.8v 2.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) f osc i dd (a)
? 2010 microchip technology inc. preliminary ds41418a-page 241 pic16f707/pic16lf707 figure 26-20: pic16lf707 maximum i dd vs. f osc over v dd , intosc mode figure 26-21: pic16f707 maximum i dd vs. f osc over v dd , intosc mode, v cap = 0.1f 1.8v 2.5v 3v 3.6v 100 110 120 130 140 150 160 170 62.5 khz 125 khz 250 khz 500 khz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) f osc i dd (a) 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2 mhz 4 mhz 8 mhz 16 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) f osc 1.8v 2.5v 5v 3.6v
pic16f707/pic16lf707 ds41418a-page 242 preliminary ? 2010 microchip technology inc. figure 26-22: pic16lf707 maximum i dd vs. f osc over v dd , intosc mode figure 26-23: pic16f707 typical i dd vs. f osc over v dd , intosc mode, v cap = 0.1f 1.8v 2.5v 3v 3.6v 0 250 500 750 1,000 1,250 1,500 1,750 2,000 2,250 2 mhz 4 mhz 8 mhz 16 mhz s typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) f osc 1.8v 2.5v 3.6v 5v 80 90 100 110 120 130 140 150 160 62.5 khz 125 khz 250 khz 500 khz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) f osc
? 2010 microchip technology inc. preliminary ds41418a-page 243 pic16f707/pic16lf707 figure 26-24: pic16lf707 typical i dd vs. f osc over v dd , intosc mode figure 26-25: pic16f707 typical i dd vs. f osc over v dd , intosc mode, v cap = 0.1f 3.6v 1.8v 2.5v 3v 70 80 90 100 110 120 130 140 62.5 khz 125 khz 250 khz 500 khz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) f osc 1.8v 2.5v 3.6v 5v 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2 mhz 4 mhz 8 mhz 16 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) f osc
pic16f707/pic16lf707 ds41418a-page 244 preliminary ? 2010 microchip technology inc. figure 26-26: pic16lf707 typical i dd vs. f osc over v dd , intosc mode figure 26-27: pic16f707 maximum base i pd vs. v dd , v cap = 0.1f 3.6v 1.8v 2.5v 3v 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2 mhz 4 mhz 8 mhz 16 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i dd (a) v dd (v) 85c 125c 0 5 10 15 20 25 1.8v 2v 3v 3.6v 4v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 245 pic16f707/pic16lf707 figure 26-28: pic16lf707 maximum base i pd vs. v dd figure 26-29: pic16f707 typical base i pd vs. v dd , v cap = 0.1f 125c 85c 0 1 2 3 4 5 6 7 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) 25c 2 3 4 5 6 7 8 1.8v 2v 3v 3.6v 4v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 246 preliminary ? 2010 microchip technology inc. figure 26-30: pic16lf707 typical base i pd vs. v dd figure 26-31: pic16f707 fixed voltage reference i pd vs. v dd , v cap = 0.1f 25c 0 50 100 150 200 250 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (na) v dd (v) typ. 25c max. 125c max. 85c 0 10 20 30 40 50 60 70 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 247 pic16f707/pic16lf707 figure 26-32: pic16lf707 fixed voltage reference i pd vs. v dd figure 26-33: pic16f707 bor i pd vs. v dd , v cap = 0.1f typ. 25c max. 125c max. 85c 0 5 10 15 20 25 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25c max. 125c max. 85c 0 10 20 30 40 50 60 70 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 248 preliminary ? 2010 microchip technology inc. figure 26-34: pic16lf707 bor i pd vs. v dd figure 26-35: pic16f707 cap sense high power i pd vs. v dd , v cap = 0.1f typ. 25c max. 125c max. 85c 0 5 10 15 20 25 30 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25c max. 125c max. 85c 0 10 20 30 40 50 60 70 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 249 pic16f707/pic16lf707 figure 26-36: pic16lf707 cap sense high power i pd vs. v dd figure 26-37: pic16f707 cap sense medium power i pd vs. v dd , v cap = 0.1f typ. 25c max. 125c max. 85c 0 10 20 30 40 50 60 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25c max. 125c max. 85c 0 5 10 15 20 25 30 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 250 preliminary ? 2010 microchip technology inc. figure 26-38: pic16lf707 cap sense medium power i pd vs. v dd figure 26-39: pic16f707 cap sense low power i pd vs. v dd , v cap = 0.1f typ. 25c max. 125c max. 85c 0 2 4 6 8 10 12 14 16 18 20 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25c max. 125c max. 85c 0 5 10 15 20 25 30 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 251 pic16f707/pic16lf707 figure 26-40: pic16lf707 cap sense low power i pd vs. v dd figure 26-41: pic16f707 t1osc 32 khz i pd vs. v dd , v cap = 0.1f typ. 25c max. 125c max. 85c 0 2 4 6 8 10 12 14 16 18 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25 c max. 85c 0 2 4 6 8 10 12 14 16 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 252 preliminary ? 2010 microchip technology inc. figure 26-42: pic16lf707 t1osc 32 khz i pd vs. v dd figure 26-43: pic16f707 typical adc i pd vs. v dd , v cap = 0.1f typ. max. 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25c 5.0 5.5 6.0 6.5 7.0 7.5 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 253 pic16f707/pic16lf707 figure 26-44: pic16lf707 typical adc i pd vs. v dd figure 26-45: pic16f707 adc i pd vs. v dd , v cap = 0.1f typ. 25c 0 50 100 150 200 250 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (na) v dd (v) max. 85c max. 125c 5 10 15 20 25 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
pic16f707/pic16lf707 ds41418a-page 254 preliminary ? 2010 microchip technology inc. figure 26-46: pic16lf707 adc i pd vs. v dd figure 26-47: pic16f707 wdt i pd vs. v dd , v cap = 0.1f max. 85c max. 125c 0 1 2 3 4 5 6 7 8 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) typ. 25c max. 85c 0 2 4 6 8 10 12 14 16 18 1.8v 2v 3v 3.6v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v)
? 2010 microchip technology inc. preliminary ds41418a-page 255 pic16f707/pic16lf707 figure 26-48: pic16lf707 wdt i pd vs. v dd figure 26-49: ttl input threshold v in vs. v dd over temperature typ. 25c max. 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.8v 2v 2.5v 3v 3.6v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) i pd (a) v dd (v) max. -40 typ. 25 min. 125 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.8 3.6 5.5 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) v in (v) v dd (v) typical: mean @25c
pic16f707/pic16lf707 ds41418a-page 256 preliminary ? 2010 microchip technology inc. figure 26-50: schmitt trigger input threshold v in vs. v dd over temperature figure 26-51: schmitt trigger input threshold v in vs. v dd over temperature v ih min. 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.8 3.6 5.5 v in (v) v dd (v) v ih max. -40c maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1.8 3.6 5.5 v in (v) v dd (v) v il min. 125c v il max. -40c maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c
? 2010 microchip technology inc. preliminary ds41418a-page 257 pic16f707/pic16lf707 figure 26-52: v oh vs. i oh over temperature, v dd = 5.5v figure 26-53: v oh vs. i oh over temperature, v dd = 3.6v max. -40 min. 125 typ. 25 5 5.1 5.2 5.3 5.4 5.5 5.6 -5.0 -4.2 -3.4 -2.6 -1.8 -1.0 -0.2 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c v oh (v) i oh (ma) 2.6 2.8 3 3.2 3.4 3.6 3.8 -5.0 -4.2 -3.4 -2.6 -1.8 -1.0 -0.2 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c v oh (v) i oh (ma) max. -40 typ. 25 min. 125
pic16f707/pic16lf707 ds41418a-page 258 preliminary ? 2010 microchip technology inc. figure 26-54: v oh vs. i oh over temperature, v dd = 1.8v figure 26-55: v ol vs. i ol over temperature, v dd = 5.5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 v oh (v) i oh (ma) max. -40 typ. 25 min. 125 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c min. -40 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 5.0 6.0 7.0 8.0 9.0 10.0 v ol (v) i ol (ma) max. 125 typ. 25 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c
? 2010 microchip technology inc. preliminary ds41418a-page 259 pic16f707/pic16lf707 figure 26-56: v ol vs. i ol over temperature, v dd = 3.6 figure 26-57: v ol vs. i ol over temperature, v dd = 1.8v min. -40 typ. 25 max. 125 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 4.0 5.0 6.0 7.0 8.0 9.0 10.0 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c v ol (v) i ol (ma) 0 0.2 0.4 0.6 0.8 1 1.2 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 maximum: mean + 3 ? (-40c to 125c) minimum: mean - 3 ? (-40c to 125c) typical: mean @25c v ol (v) i ol (ma) max. 125 min. -40
pic16f707/pic16lf707 ds41418a-page 260 preliminary ? 2010 microchip technology inc. figure 26-58: pic16f707 pwrt period figure 26-59: pic16f707 wdt time-out period max. -40c min. 125c 45 55 65 75 85 95 105 1.8v 2v 2.2v 2.4v 3v 3.6v 4v 4.5v 5v 5.5v time (ms) v dd typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) typ. 25c typ. 25c max. -40c min. 125c 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 1.8v 2v 2.2v 2.4v 3v 3.6v 4v 4.5v 5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) time (ms) v dd
? 2010 microchip technology inc. preliminary ds41418a-page 261 pic16f707/pic16lf707 figure 26-60: pic16f707 hfintosc wake-up from sleep start-up time figure 26-61: pic16f707 a/d internal rc oscillator period max. typ. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.8v 2v 3v 3.6v 4v 4.5v 5v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) time (us) v dd max. min. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8v 3.6v 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) period (s) v dd (v)
pic16f707/pic16lf707 ds41418a-page 262 preliminary ? 2010 microchip technology inc. figure 26-62: pic16f707 cap sense ou tput current, power mode = high figure 26-63: pic16f707 cap sense ou tput current, power mode = medium -15000 -10000 -5000 0 5000 10000 15000 20000 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 current (na) v dd (v) min. sink -40c typ. sink 25c max. sink 85c min. source 85c typ. source 25c max. source -40c -3000 -2000 -1000 0 1000 2000 3000 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 current (na) v dd (v) max. sink -40c typ. sink 25c min. sink 85c min. source 85c typ. source 25c max. source -40c
? 2010 microchip technology inc. preliminary ds41418a-page 263 pic16f707/pic16lf707 figure 26-64: pic16f707 cap sense ou tput current, power mode = low figure 26-65: pic16f707 cap sensor hysteresis, power mode = high -800 -600 -400 -200 0 200 400 600 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 current (na) v dd (v) max. sink 85c typ. sink 25c min. sink -40c min. source 85c typ. source 25c max. source -40c 300 400 500 600 700 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 max. 125c max. 85c typ. 25c min. 0c min. -40c mv v dd (v)
pic16f707/pic16lf707 ds41418a-page 264 preliminary ? 2010 microchip technology inc. figure 26-66: pic16f707 cap sensor hysteresis, power mode = medium figure 26-67: pic16f707 cap sensor hysteresis, power mode = low 250 300 350 400 450 500 550 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 max. 125c typ. 25c min. 0c min. -40c mv v dd (v) max. 85c 150 200 250 300 350 400 450 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 max. 125c max. 85c typ. 25c min. 0c mv v dd (v) min -40c
? 2010 microchip technology inc. preliminary ds41418a-page 265 pic16f707/pic16lf707 figure 26-68: typical fvr (x1 and x2) vs. supply voltage (v) normalized at 3.0v figure 26-69: typical fvr change vs. temperature norm alized at 25c -1.5 -1 -0.5 0 0.5 1 1.5 1.8 2.5 3 3.6 4.2 5.5 voltage percent change (%) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 -40 0 45 85 125 temperature (c) percent change (%)
pic16f707/pic16lf707 ds41418a-page 266 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 267 pic16f707/pic16lf707 27.0 packaging information 27.1 package marking information * standard picmicro ? device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn example pic16f707 10033k1 -i/p 3 e xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn example pic16f707 -i/ml 10033k1 44-lead tqfp xxxxxxxxxxx xxxxxxxxxxx xxxxxxxxxxx yywwnnn example pic16f707 10033k1 -i/pt 3 e
pic16f707/pic16lf707 ds41418a-page 268 preliminary ? 2010 microchip technology inc. 27.2 package details the following sections give the technical details of the packages.

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? 2010 microchip technology inc. preliminary ds41418a-page 273 pic16f707/pic16lf707 appendix a: data sheet revision history revision a (april 2010) original release of this data sheet. appendix b: migrating from other pic ? devices this discusses some of the issues in migrating from other pic ? devices to the pic16f707 family of devices. b.1 pic16f77 to pic16f707 note: this device has been designed to perform to the parameters of its data sheet. it has been tested to an electrical specification designed to determine its conformance with these parameters. due to process differences in the manufacture of this device, this device may have different performance characteristics than its ealier version. these differences may cause this device to perform differently in your application than the earlier version of this device. note: the user should verify that the device oscillator starts and performs as expected. adjusting the loading capacitor values and/or the oscillator mode may be required. table b-1: feature comparison feature pic16f77 pic16f707 max. operating speed 20 mhz 20 mhz max. program memory (words) 8k 8k max. sram (bytes) 368 363 a/d resolution 8-bit 8-bit timers (8/16-bit) 2/1 4/2 oscillator modes 4 8 brown-out reset y y internal pull-ups rb<7:0> rb<7:0> interrupt-on-change rb<7:4> rb<7:0> comparator 0 0 usart y y extended wdt n n software control option of wdt/bor nn intosc frequencies none 500 khz - 16 mhz clock switching n n
pic16f707/pic16lf707 ds41418a-page 274 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 275 pic16f707/pic16lf707 index a a/d specifications.................................................... 220, 221 absolute maximum ratings .............................................. 201 ac characteristics industrial and extended ............................................ 212 load conditions ........................................................ 211 adc .................................................................................... 79 acquisition requirements ........................................... 86 associated registers.................................................... 88 block diagram............................................................. 79 calculating acquisition time....................................... 86 channel selection....................................................... 80 configuration............................................................... 80 configuring interrupt ................................................... 82 conversion clock........................................................ 80 conversion procedure ................................................ 82 internal sampling switch (r ss ) i mpedance ................ 86 interrupts..................................................................... 81 operation .................................................................... 82 operation during sleep .............................................. 82 port configuration ....................................................... 80 reference voltage (v ref )........................................... 80 source impedance...................................................... 86 special event trigger.................................................. 82 adcon0 register......................................................... 19, 84 adcon1 register......................................................... 20, 85 addressable universal synchronous asynchronous receiver transmitter (ausart)............................... 137 adres register ................................................................. 85 adresh register............................................................... 19 alternate pin function......................................................... 51 analog-to-digital converter. see adc ansela register ............................................................... 53 anselb register ......................................................... 57, 60 anseld register ............................................................... 63 ansele register ............................................................... 66 apfcon register............................................................... 51 assembler mpasm assembler................................................... 198 ausart ........................................................................... 137 associated registers baud rate generator........................................ 147 asynchronous mode ................................................. 139 associated registers receive..................................................... 144 transmit.................................................... 141 baud rate generator (brg) ............................ 147 receiver............................................................ 141 setting up 9-bit mode with address detect....... 143 transmitter........................................................ 139 baud rate generator (brg) baud rate error, calculating ............................ 147 formulas ........................................................... 147 high baud rate select (brgh bit) .................. 147 synchronous master mode ............................... 150, 154 associated registers receive..................................................... 153 transmit.................................................... 151 reception.......................................................... 152 transmission .................................................... 150 synchronous slave mode associated registers receive .................................................... 155 transmit ................................................... 154 reception ......................................................... 155 transmission .................................................... 154 b bf bit ........................................................................ 165, 177 block diagrams (ccp) capture mode operation ............................... 129 adc ............................................................................ 79 adc transfer function ............................................... 87 analog input model..................................................... 87 ausart receive ..................................................... 138 ausart transmit .................................................... 137 ccp pwm ................................................................ 133 clock source .............................................................. 69 compare................................................................... 131 crystal operation........................................................ 73 digital-to-analog converter (dac) ............................. 92 external rc mode ...................................................... 74 interrupt logic............................................................. 39 mclr circuit .............................................................. 31 on-chip reset circuit................................................. 29 resonator operation .................................................. 74 spi mode.................................................................. 158 ssp (i 2 c mode)........................................................ 167 timer1 ...................................................................... 100 timer2 ...................................................................... 115 tmr0/wdt prescaler ........................................ 95, 111 voltage reference...................................................... 92 voltage reference output buffer example ................ 92 brown-out reset (bor)...................................................... 33 specifications ........................................................... 218 timing and characteristics ....................................... 217 c c compilers mplab c18 .............................................................. 198 capacitive sensing ........................................................... 117 capture module. see capture/compare/pwm (ccp) capture/compare/pwm (ccp) ........................................ 127 associated registers w/ capture............................... 130 associated registers w/ compare............................. 132 associated registers w/ pwm................................... 136 capture mode ........................................................... 129 ccpx pin configuration............................................ 129 compare mode ......................................................... 131 ccpx pin configuration.................................... 131 software interrupt mode ........................... 129, 131 special event trigger ....................................... 131 timer1 mode selection............................. 129, 131 interaction of two ccp modules (table)................... 127 prescaler .................................................................. 129 pwm mode............................................................... 133 duty cycle ........................................................ 134 effects of reset ................................................ 135 example pwm frequencies and resolutions, 20 mhz ................................ 135 example pwm frequencies and resolutions, 8 mhz .................................. 135 operation in sleep mode.................................. 135 setup for operation .......................................... 135 system clock frequency changes .................. 135 pwm period ............................................................. 134
pic16f707/pic16lf707 ds41418a-page 276 preliminary ? 2010 microchip technology inc. setup for pwm operation ......................................... 135 timer resources....................................................... 127 ccp. see capture/compare/pwm (ccp) ccp1con register ............................................................ 19 ccp2con register ............................................................ 19 ccpr1h register ............................................................... 19 ccpr1l register................................................................ 19 ccpr2h register ............................................................... 19 ccpr2l register................................................................ 19 ccpxcon register .......................................................... 128 cke bit ...................................................................... 165, 177 ckp bit ...................................................................... 164, 176 clock sources external modes ........................................................... 73 ec ....................................................................... 73 hs ....................................................................... 73 lp........................................................................ 73 ost..................................................................... 73 rc....................................................................... 74 xt ....................................................................... 73 code examples a/d conversion ........................................................... 83 call of a subroutine in page 1 from page 0................ 26 changing between capture prescalers .................... 129 indirect addressing ..................................................... 27 initializing porta....................................................... 52 initializing portb....................................................... 55 initializing portc....................................................... 59 initializing portd....................................................... 62 initializing porte....................................................... 65 loading the sspbuf (sspsr) register .................. 160 saving w, status and pclath registers in ram ............................................................... 41 compare module. see capture/compare/pwm (ccp) config1 register........................................................ 75, 76 customer change notification service ............................. 281 customer notification service........................................... 281 customer support ............................................................. 281 d d/a bit ............................................................................... 177 daccon0 (digital-to-analog converter control 0) register....................................................................... 93 daccon1 (digital-to-analog converter control 1) register....................................................................... 93 data memory....................................................................... 17 data/address bit (d/a ) ...................................................... 177 dc and ac characteristics ............................................... 231 dc characteristics extended and industrial ............................................ 208 industrial and extended ............................................ 202 development support ....................................................... 197 device configuration........................................................... 75 code protection .......................................................... 77 configuration word ..................................................... 75 user id ........................................................................ 77 device overview ................................................................. 11 digital-to-analog converter (dac)...................................... 91 associated registers .................................................. 94 effects of a reset........................................................ 91 operation during sleep .............................................. 91 e eecon1 register ............................................................... 22 effects of reset pwm mode ............................................................... 135 electrical specifications .................................................... 201 enhanced capture/compare/pwm (eccp) specifications ........................................................... 220 errata .................................................................................... 9 f firmware instructions ....................................................... 187 fixed voltage reference. see fvr fsr register ................................................................ 19, 20 fuses. see configuration bits fvr..................................................................................... 89 fvrcon register .............................................................. 90 g general purpose register file ........................................... 17 i i 2 c mode associated registers ................................................ 178 indf register ............................................................... 19, 20 indirect addressing, indf and fsr registers ................... 27 instruction format............................................................. 187 instruction set................................................................... 187 addlw..................................................................... 189 addwf..................................................................... 189 andlw..................................................................... 189 andwf..................................................................... 189 movf ....................................................................... 192 bcf .......................................................................... 189 bsf........................................................................... 189 btfsc ...................................................................... 189 btfss ...................................................................... 190 call......................................................................... 190 clrf ........................................................................ 190 clrw ....................................................................... 190 clrwdt .................................................................. 190 comf ....................................................................... 190 decf ........................................................................ 190 decfsz ................................................................... 191 goto ....................................................................... 191 incf ......................................................................... 191 incfsz..................................................................... 191 iorlw ...................................................................... 191 iorwf...................................................................... 191 movlw .................................................................... 192 movwf .................................................................... 192 nop .......................................................................... 192 retfie ..................................................................... 193 retlw ..................................................................... 193 return................................................................... 193 rlf ........................................................................... 194 rrf .......................................................................... 194 sleep ...................................................................... 194 sublw ..................................................................... 194 subwf..................................................................... 195 swapf ..................................................................... 195 xorlw .................................................................... 195 xorwf .................................................................... 195 summary table ........................................................ 188 intcon register................................................................ 42 internal oscillator block intosc specifications ................................................... 215 internal sampling switch (r ss ) i mpedance ........................ 86 internet address ............................................................... 281 interrupts............................................................................. 39
? 2010 microchip technology inc. preliminary ds41418a-page 277 pic16f707/pic16lf707 adc ............................................................................ 82 associated registers w/ interrupts............................... 47 configuration word w/ ldo ........................................ 49 interrupt-on-change.................................................... 55 synchronous serial port interrupt............................... 46 intosc specifications ..................................................... 215 iocb register..................................................................... 57 l load conditions ................................................................ 211 m mclr .................................................................................. 31 internal ........................................................................ 31 memory organization.......................................................... 17 data ............................................................................ 17 program ...................................................................... 17 microchip internet web site .............................................. 281 migrating from other pic microcontroller devices............. 273 mplab asm30 assembler, linker, librarian ................... 198 mplab integrated development environment software .. 197 mplab pm3 device programmer .................................... 200 mplab real ice in-circuit emulator system................. 199 mplink object linker/mplib object librarian ................ 198 o opcode field descriptions ............................................. 187 option register................................................................ 24 option_reg register ...................................................... 97 osccon register.............................................................. 71 oscillator associated registers............................................ 74, 115 oscillator module ec ............................................................................... 69 hs ............................................................................... 69 intosc ...................................................................... 69 intoscio................................................................... 69 lp................................................................................ 69 oscillator tuning ......................................................... 72 rc............................................................................... 69 rcio ........................................................................... 69 xt ............................................................................... 69 oscillator parameters ....................................................... 215 oscillator specifications.................................................... 214 oscillator start-up timer (ost) specifications............................................................ 218 osctune register ............................................................ 72 p p (stop) bit ........................................................................ 177 packaging ......................................................................... 267 marking ..................................................................... 267 pdip details.............................................................. 268 paging, program memory ................................................... 26 pcl and pclath ............................................................... 26 computed goto........................................................ 26 stack ........................................................................... 26 pcl register................................................................. 19, 20 pclath register ......................................................... 19, 20 pcon register ....................................................... 20, 25, 34 pie1 register................................................................ 20, 43 pie2 register...................................................................... 20 pinout descriptions pic16f707/pic16lf707............................................. 13 pir1 register................................................................ 19, 45 pir2 register................................................................ 19, 46 pmadrh register............................................................ 181 pmadrl register ............................................................ 181 pmcon1 register .................................................... 180, 181 pmdath register ............................................................ 180 pmdatl register............................................................. 180 porta ............................................................................... 52 ansela register ....................................................... 53 associated registers.................................................. 54 pin descriptions and diagrams .................................. 53 porta register......................................................... 19 ra0............................................................................. 53 ra3............................................................................. 54 ra4............................................................................. 54 ra5............................................................................. 54 ra6............................................................................. 54 ra7............................................................................. 54 specifications ........................................................... 216 porta register ................................................................. 52 portb ............................................................................... 55 additional pin functions anselb register ................................... 55, 60, 65 weak pull-up ...................................................... 55 associated registers.................................................. 58 interrupt-on-change ................................................... 55 p1b/p1c/p1d. see enhanced capture/compare/ pwm+ (eccp+) ................................................. 55 pin descriptions and diagrams .................................. 57 portb register......................................................... 19 rb0............................................................................. 57 rb1............................................................................. 57 rb2............................................................................. 57 rb3............................................................................. 58 rb4............................................................................. 58 rb5............................................................................. 58 rb6............................................................................. 58 rb7............................................................................. 58 portb register ................................................................. 56 portc ............................................................................... 59 associated registers.................................................. 61 p1a. see enhanced capture/compare/pwm+ (eccp+) ............................................................. 59 portc register......................................................... 19 rc0 ............................................................................ 60 rc2 ............................................................................ 61 rc3 ............................................................................ 61 rc4 ............................................................................ 61 rc5 ............................................................................ 61 rc6 ............................................................................ 61 rc7 ............................................................................ 61 specifications ........................................................... 216 portc register................................................................. 59 portd ............................................................................... 62 additional pin functions anseld register............................................... 62 associated registers.................................................. 64 p1b/p1c/p1d. see enhanced capture/compare/ pwm+ (eccp+) ................................................. 62 portd register......................................................... 19 rd6 ...................................................................... 63, 64 portd register................................................................. 62 porte ............................................................................... 65 associated registers.................................................. 67 porte register......................................................... 19 re0............................................................................. 66 re1............................................................................. 66
pic16f707/pic16lf707 ds41418a-page 278 preliminary ? 2010 microchip technology inc. re2 ............................................................................. 66 re3 ............................................................................. 67 porte register ................................................................. 65 power-down mode (sleep) ............................................... 183 associated registers ................................................ 184 power-on reset .................................................................. 31 power-up timer (pwrt)..................................................... 31 specifications............................................................ 218 pr2 register............................................................... 20, 166 precision internal oscillator parameters........................... 215 prescaler shared wdt/timer0 ........................................... 96, 112 product identification system............................................ 283 program .............................................................................. 17 program memory ................................................................ 17 map and stack (pic16f707/pic16lf707) ................. 17 paging ......................................................................... 26 program memory read (pmr) ......................................... 179 associated registers ................................................ 181 programming, device instructions .................................... 187 r r/w bit .............................................................................. 177 rcreg ............................................................................. 143 rcreg register................................................................. 19 rcsta register.......................................................... 19, 146 reader response ............................................................. 282 read-modify-write operations.......................................... 187 receive overflow indicator bit (sspov)................... 164, 176 registers adcon0 (adc control 0) .......................................... 84 adcon1 (adc control 1) .......................................... 85 adres (adc result) ................................................. 85 ansela (porta analog select)............................... 53 anselb (portb analog select)......................... 57, 60 anseld (portd analog select) .............................. 63 ansele (porte analog select)............................... 66 apfcon (alternate pin function control).................. 51 ccpxcon (ccp operation) ..................................... 128 config1 (configuration word register 1) .......... 75, 76 daccon0 .................................................................. 93 daccon1 .................................................................. 93 fvrcon (fixed voltage reference register) ........... 90 intcon (interrupt control) ......................................... 42 iocb (interrupt-on-change portb) .......................... 57 option_reg (option) ........................................... 24 option_reg (option) .............................................. 97 osccon (oscillator control) ..................................... 71 osctune (oscillator tuning) .................................... 72 pcon (power control register) ................................. 25 pcon (power control) ............................................... 34 pie1 (peripheral interrupt enable 1) ........................... 43 pir1 (peripheral interrupt register 1) ........................ 45 pir2 (peripheral interrupt request 2) ........................ 46 pmadrh (program memory address high)............. 181 pmadrl (program memory address low) .............. 181 pmcon1 (program memory control 1) .................... 180 pmdath (program memory data high)................... 180 pmdatl (program memory data low) .................... 180 porta........................................................................ 52 portb........................................................................ 56 portc ....................................................................... 59 portd ....................................................................... 62 porte........................................................................ 65 rcsta (receive status and control)....................... 146 reset values............................................................... 36 reset values (special registers) ............................... 38 sspcon (sync serial port control) register .. 164, 176 sspstat (sync serial port status) register... 165, 177 status ..................................................................... 23 t2con ..................................................................... 116 trisa (tri-state porta)........................................... 52 trisb (tri-state portb)........................................... 56 trisc (tri-state portc) .......................................... 59 trisd (tri-state portd) .......................................... 63 trise (tri-state porte)........................................... 66 txsta (transmit status and control) ...................... 145 wpub (weak pull-up portb)................................... 56 reset .................................................................................. 29 resets associated registers .................................................. 38 revision history................................................................ 273 s s (start) bit........................................................................ 177 smp bit ..................................................................... 165, 177 software simulator (mplab sim) .................................... 199 spbrg ............................................................................. 147 spbrg register................................................................. 20 special event trigger ......................................................... 82 special function registers ................................................. 17 spi mode .......................................................................... 163 associated registers ................................................ 166 typical master/slave connection ............................. 157 ssp................................................................................... 157 i 2 c mode .................................................................. 167 acknowledge .................................................... 168 addressing........................................................ 169 clock stretching ............................................... 174 clock synchronization ...................................... 175 firmware master mode..................................... 174 hardware setup................................................ 167 multi-master mode............................................ 174 reception ......................................................... 170 sleep operation................................................ 175 start/stop conditions........................................ 168 transmission .................................................... 172 master mode............................................................. 158 spi mode .................................................................. 157 slave mode....................................................... 161 typical spi master/slave connection ...................... 157 sspadd register............................................................... 20 sspbuf register ............................................................... 19 sspcon register .............................................. 19, 164, 176 sspen bit................................................................. 164, 176 sspif ................................................................................. 46 sspm bits ................................................................. 164, 176 sspov bit................................................................. 164, 176 sspstat register ............................................. 20, 165, 177 status register ............................................................... 23 synchronous serial port enable bit (sspen) .......... 164, 176 synchronous serial port interrupt....................................... 46 synchronous serial port mode select bits (sspm).. 164, 176 t t1con register ........................................................... 19, 20 t2con register ................................................. 19, 116, 166 thermal considerations.................................................... 210 time-out sequence ............................................................ 34 timer0................................................................................. 95 associated registers .......................................... 97, 113 interrupt ...................................................................... 97
? 2010 microchip technology inc. preliminary ds41418a-page 279 pic16f707/pic16lf707 operation .................................................... 96, 101, 112 specifications............................................................ 219 timer1 ................................................................................. 99 asynchronous counter mode ................................... 102 reading and writing ......................................... 102 modes of operation .................................................. 101 oscillator ................................................................... 102 prescaler................................................................... 102 specifications............................................................ 219 tmr1h register ......................................................... 99 tmr1l register.......................................................... 99 timer2 associated registers.................................................. 116 timers timer2 t2con.............................................................. 116 timing diagrams a/d conversion......................................................... 221 a/d conversion (sleep mode) .................................. 222 asynchronous reception .......................................... 144 asynchronous transmission..................................... 140 asynchronous transmission (back-to-back) ............ 140 brown-out reset (bor) ............................................ 217 brown-out reset situations ........................................ 33 clkout and i/o....................................................... 215 clock synchronization .............................................. 175 clock timing ............................................................. 212 enhanced capture/compare/pwm (eccp) ............. 220 i 2 c bus data ............................................................. 227 i 2 c bus start/stop bits.............................................. 226 i 2 c reception (7-bit address) ................................... 170 i 2 c slave mode with sen = 0 (reception, 10-bit address) ................................................. 171 i 2 c transmission (7-bit address).............................. 172 int pin interrupt.......................................................... 40 reset, wdt, ost and power-up timer ................... 217 slave select synchronization ................................... 163 spi master mode ...................................................... 160 spi master mode (cke = 1, smp = 1) ..................... 224 spi mode (slave mode with cke = 0) ...................... 162 spi mode (slave mode with cke = 1) ...................... 162 spi slave mode (cke = 0) ....................................... 224 spi slave mode (cke = 1) ....................................... 225 synchronous reception (master mode, sren) ....... 153 synchronous transmission....................................... 151 synchronous transmission (through txen) ........... 151 time-out sequence case 1 ................................................................ 34 case 2 ................................................................ 35 case 3 ................................................................ 35 timer0 and timer1 external clock ........................... 219 usart synchronous receive (master/slave) ......... 223 usart synchronous transm ission (master/slave) . 222 wake-up from interrupt ............................................. 184 timing parameter symbology........................................... 211 timing requirements i 2 c bus data ............................................................. 228 i2c bus start/stop bits ............................................. 227 spi mode .................................................................. 226 tmr0 register.................................................................... 19 tmr1h register ........................................................... 19, 20 tmr1l register............................................................ 19, 20 tmr2 register.................................................................... 19 tmro register ................................................................... 21 trisa ................................................................................. 52 trisa register............................................................. 20, 52 trisb ................................................................................. 55 trisb register............................................................. 20, 56 trisc ................................................................................. 59 trisc register............................................................. 20, 59 trisd ................................................................................. 62 trisd register............................................................. 20, 63 trise ................................................................................. 65 trise register............................................................. 20, 66 txreg ............................................................................. 139 txreg register ................................................................. 19 txsta register.......................................................... 20, 145 brgh bit .................................................................. 147 u ua..................................................................................... 177 update address bit, ua .................................................... 177 usart synchronous master mode requirements, synchronous receive .............. 223 requirements, synchronous transmission...... 222 timing diagram, synchronous receive ........... 223 timing diagram, synchronous transmission... 222 v v ref . s ee adc reference voltage w wake-up using interrupts ................................................. 184 watchdog timer (wdt)...................................................... 31 clock source .............................................................. 31 modes......................................................................... 32 period ......................................................................... 31 specifications ........................................................... 218 wcol bit .................................................................. 164, 176 wpub register................................................................... 56 write collision detect bit (wcol) ............................ 164, 176 www address ................................................................. 281 www, on-line support ..................... .................................. 9
pic16f707/pic16lf707 ds41418a-page 280 preliminary ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. preliminary ds41418a-page 281 pic16f707/pic16lf707 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic16f707/pic16lf707 ds41418a-page 282 preliminary ? 2010 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41418a pic16f707/pic16lf707 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2010 microchip technology inc. preliminary ds41418a-page 283 pic16f707/pic16lf707 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f707, pic16lf707, pic16f707t, pic16lf707t (1) temperature range: i= -40 ? c to +85 ? c e= -40 ? c to +125 ? c package: mv = micro lead frame (uqfn) ml = micro lead frame (qfn) p = plastic dip pt = tqfp (thin quad flatpack) pattern: 3-digit pattern code for qtp (blank otherwise) examples: a) pic16f707-e/p 301 = extended temp., pdip package, qtp pattern #301 b) pic16f707-i/ml = industrial temp., qfn package note 1: t = in tape and reel.
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